Abstract: An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms.

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.

Abstract: A programmable sequencer 10 uses an input mapping circuit 20 including a programmable logic array 30 to map decision variable input conditions onto branch address signals, which are used with primary address signals to form a next state address for state word memory 50. Input mapping circuit 20 preferably includes a branch control circuit 40, controlled by feedback signals from the output of state word memory 50, to selectively transform branch address signals to allow different states to use state word locations sharing the same primary address in state word memory 50. The preferred embodiment also includes a diagnostic circuit 80 useful for programming, and/or diagnosing operation of, sequencer 10.

Abstract: In order to prevent bonding wire sag and to allow high lead count an insulative bridging member is provided between the ends of inner leads of a lead frame and a centrally mounted integrated circuit die. The bridging member of annular square configuration has transverse plated spaced conductive pathways. A first series of short bonding wires connect selected die contact pads to an inner end of selected conductive pathways and a second concentric series of bonding wires connect an outer end of the selective conductive pathways of the bridging member to selected ones of the inner leads of the lead frame. The above elements except for outer leads of the lead frame are encapsulated to form an overall die package with external leads or pin contacts.

Abstract: A method for forming a titanium tungsten fuse begins with the steps of forming a silicon dioxide layer (42), a titanium tungsten layer (44) and a aluminum layer (46) on a silicon substrate (40). The titanium tungsten layer serves as fuse material while the aluminum layer serves as interconnect material. A photolithographic mask (48) is then applied to the wafer. The portion of the aluminum layer exposed by the photolithographic mask and the portion of the titanium tungsten layer lying thereunder are then removed. Because both the aluminum and titanium tungsten layers are etched simultaneously, a dry etching process can be used during this step. The resulting structure includes a thin aluminum and titanium tungsten region where the resulting fuse is to be formed. Thereafter, the first photolithographic mask is removed and a second photolithographic mask is applied to the wafer which includes a window region where the titanium tungsten fuse is to formed.

Abstract: An emitter coupled logic circuit includes a bypass circuit which provides a conductive path for current when a programmable fuse is blown, so that input data is transmitted independently of the state of a clock signal. In one implementation, the circuit takes a register configuration having a master section and a slave section, each incorporating a programmable fuse. When the fuse in just one section is intact, the circuit serves as a clocked latch. When both fuses are blown, the bypass circuit is enabled so that the register functions as a combinatorial circuit which produces an output signal dependent on the input signal without reference to a clock signal.

Abstract: A structure for isolating a bipolar transistor (100) from an adjacent transistor includes a first silicon dioxide isolation region (110) laterally surrounding the transistor and a conductive channel stop region (112) laterally surrounding the silicon dioxide isolation region. The channel stop region allows electrical potential of the substrate (102) to be controlled and the silicon dioxide isolation region prevents the channel stop from contacting the transistor.

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

Abstract: A TTL inverting output circuit (50) which uses the collector (65) of a parallel phase splitter transistor (Q11) where the voltage changes in phase with the circuit output signal Io to control an active circuit (70) which diverts charge from the base (23) of the output pull-down transistor (Q3).

Abstract: A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.

Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.

Abstract: Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.

Abstract: A programmable read-only memory (40) is provided which is capable of storing a plurality of initialize words. The memory includes an initialize input lead (9) and appropriate addressing circuitry (7) so that when the appropriate initialize input signal is placed on the initialize input lead, one of several pre-programmed initialize words is placed in the output register (6) of the programmable read-only memory. The word that is placed in the output register is selected according to signals applied to selected address input leads (A.sub.0 through A.sub.3) of the programmable read-only memory. The number of address input signals utilized to determine which initialize word is placed in the output register of the programmable read-only memory is a selected subset of the available address input signals provided to the memory. The described embodiment provides sixteen initialize words using a minimum number of components.

Abstract: A current source for powering programmable arrays which provides means of eliminating the current supplied to portions of the array which are unimportant to the boolean arithmetic equation which the programmable array is programmed to model. The circuit includes fusible links (33-1 through 33-M) between the current source and portions of the circuit which may be unnecessary. Also included is means of opening (13-1 through 13-M) the fusible links (33-1 through 33-M) which connect the current source with the elements of the programmable array which may be unnecessary, thereby saving the power used to generate the current which would have been wasted in driving the unnecessary portions of the programmable array.

Abstract: A high speed M-stack fall-through FIFO memory system is disclosed which reduces fall-through delay and which permits at least a doubling of the maximum shift rates at input and output ports. Input port data may be entered in one of M physical memory locations and output port data may be read from one of M physical memory locations.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a reference fusible link to detect the presence or absence of a short circuit.

Abstract: A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. The resistance of each corresponding link in each of the four quandrants in the array is compared with the resistance of an array of reference fusible links to detect the presence or absence of a short circuit.

Abstract: A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a.c. and verification testing takes place under the same conditions, i.e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.