Abstract: The present invention discloses an off-line regulator. The off-line regulator comprises a rectification circuit configured to rectify an AC line voltage into a rectified line voltage; a pass device coupled between the rectified line voltage and a first capacitor, the pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into a converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.

Abstract: The present disclosure discloses a power system with hot-swap with a buck converter. The power system comprises a front stage, a hot-swap stage and a load stage; wherein the hot-swap stage comprises: a buck converter having a switch operate at ON/OFF state to provide a desired output voltage to the load stage with low power loss and optimized thermal design.

Abstract: The present disclosure discloses a switching mode power supply with bi-direction buck and boost control. The switching mode power supply enters boost mode when an input signal is higher than a preset threshold to pump the input signal to a higher level; and the switching mode power supply enters buck mode when the input signal breaks down to release the stored energy.

Abstract: Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.

Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.

Abstract: The present disclosure discloses an EMI capacitor discharger with an active capacitor bleeder which monitors a utility AC source and detects the zero crossing of the utility AC source. When a prolonged period of no zero crossing occurred, the EMI capacitor discharger activates a discharging circuit.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: The embodiments of the present invention illustrate a means for digitally controlling a converter system and associated method. Wherein the means for digitally controlling a converter system comprises a means for generating a digital error signal according to an output voltage of the converter system and a reference voltage, a means for generating a digital control signal according to a digital reference signal and the digital error signal, and a means for generating a PWM signal according to the digital control signal in order to control the converter system. The means for digitally controlling a converter system and associated method at least alleviate the problem of limit-cycle oscillation, and promote the performance of system transient response and accuracy.

Abstract: The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.

Abstract: The present disclosure discloses a lateral transistor and associated method for making the same. The lateral transistor comprises a gate formed over a first portion of a thin gate dielectric layer, and a field plate formed over a thick field dielectric layer and extending atop a second portion of the thin gate dielectric layer. The field plate is electrically isolated from the gate by a gap overlying a third portion of the thin gate dielectric layer and is electrically coupled to a source region. The lateral transistor according to an embodiment of the present invention may have reduced gate-to-drain capacitance, low specific on-resistance, and improved hot carrier lifetime.

Abstract: The present invention discloses a multi-phase switch-mode power supply (SMPS). The multi-phase SMPS may comprise a plurality of comparing circuits and a controller. Wherein each comparing circuit comprises a first input coupled to a threshold voltage, a second input coupled to a feedback signal of the output voltage, and an output configured to provide a load indication signal. The controller may have a plurality of inputs coupled to the outputs of the comparing circuit, and a plurality of outputs configured to provide control signals for driving a plurality of switches of the multi-phase SMPS. And the controller is configured to selectively turn on a plurality of the switches according to the load indication signals.

Abstract: A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode.

Abstract: The present technology is directed to class G audio amplifiers and the associated methods of operation. In one embodiment, a class G audio amplifier includes an input port, an audio output stage, a level detector, and a charge pump. The class G audio amplifier regulates the power supplies of the audio output stage according to the input signal, so as to realize high efficiency and high quality audio output.

Abstract: The present technology discloses a multi-die package. The package comprises a lead frame structure and three dies including a first flip chip die, a second flip chip die and a third flip chip die stacked vertically. The first flip chip die is mounted on the bottom surface of the lead frame structure through the flip chip bumps; the second flip chip is mounted on the top surface of the first flip chip die through flip chip bumps; and the third flip chip die is mounted on the top surface of the lead frame structure through flip chip bumps.

Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.

Abstract: The present technology is generally related to Triac dimmer compatible driving circuits and methods thereof. The present technology also provides an electronic transformer that is integrated in the Traic dimmer compatible driving circuit. In one embodiment, the electronic transformer detects the conduction angles of an output AC voltage from the Triac dimmer and converts said output AC voltage into a PWM DC voltage having a duty cycle regulated by said conduction angles. Said PWM DC voltage is then applied to a WLED driver for driving a WLED.

Abstract: A switching regulator that decreases power loss and resolves thermal issues by jumping its switching frequency to a maximum frequency when its load reaches a peak load.

Abstract: AC/DC power converters having an under voltage lockout circuit with first and second thresholds and associated methods of operation are disclosed herein. In one embodiment, the first threshold is greater than the second threshold. The under voltage lockout circuit is configured to enable a current source to charge the capacitor when the voltage across the capacitor is less than the second threshold. The under voltage lockout circuit is configured to shut off the current source and to enable a pulse width modulator circuit to switch a transistor when the voltage is greater than the first threshold.

Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Abstract: Triac dimmer compatible switching mode power supplies used as LED drivers are disclosed herein. A PFC controller is configured in the switching mode power supplies. With the PFC controller, the current keeping the triac in the on-state is supplied by the DC/DC converter, and the LC resonance is reduced.