Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

Abstract: A supply voltage generating circuit and method for a power system. The power system has a power input terminal to receive an input voltage, a system output terminal to provide a system voltage, a switching circuit, a bootstrap capacitor, and a first driver circuit with a power terminal. The switching circuit works in a buck mode to convert the input voltage to the system voltage, or in a boost mode to convert the system voltage to a boost output voltage. The bootstrap capacitor provides a bootstrap voltage at a bootstrap terminal. The method is generating an input pump voltage based on the input voltage and the boost output voltage, generating a first supply voltage based on the bootstrap voltage and the input pump voltage, and providing the first supply voltage to the power terminal of the first driver circuit.

Abstract: A novel converter circuit topology is disclosed. The converter circuit has a bridge circuit, a transformer, and a half-bridge current-doubler rectifier. An input end of the bridge circuit is connected to an input voltage node of the converter circuit. A reference end of the bridge circuit is connected to an output voltage node of the converter circuit. Opposing ends of a primary winding of the transformer are connected to bridge nodes of the bridge circuit. A secondary winding of the transformer serves as current-doubler inductors of the half-bridge current-doubler rectifier. A tap of the secondary winding is connected to the reference end of the bridge circuit.

Abstract: A preprocessing circuit for a comparator has a high voltage selection circuit, a first constant voltage circuit, a second constant voltage circuit, a first transistor, and a second transistor. The high voltage selection circuit receives a first voltage and a second voltage, and provides a selected voltage. The first constant voltage circuit provides a first clamping voltage based on the selected voltage, and the second constant voltage circuit provides a second clamping voltage based on the selected voltage. The first transistor receives the first voltage and the first clamping voltage, and provides a first comparison voltage to a first comparison terminal of the comparator. The second transistor receives the second voltage and the second clamping voltage, and provides a second comparison voltage to a second comparison terminal of the comparator.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a back protective film attached to a second surface of the IC die. The back protective film may have good UV sensitivity to change from non-solid to solid after UV irradiation while maintaining its viscosity with the IC die not reduced after UV irradiation. The back protective film may be uneasy to deform and to peel off from the IC die and can provide physical protection and effective heat dissipation path to the IC die.

Abstract: A USB power supply circuit is discussed. The circuit has at least two power converters and a controller. The controller controls the power converters to provide required output powers to devices attached to the controller and monitors the provided output powers. If one of the power converters has an idle power margin, the idle power margin would be distributed to other power converters.

Abstract: A drive circuit configured to drive a power stage including a high voltage power switch device. The drive circuit has a transmitter configured to send a control signal, and a receiver configured to transfer a received signal to a drive signal by a first isolated capacitor loop and a second isolated capacitor loop. The first isolated capacitor loop has a same area as the second isolated capacitor loop.

Abstract: A noise control circuit of a switching mode power supply is disclosed. The switching mode power supply has a primary switch, a secondary switch and a transformer with a primary winding and a secondary winding. The noise control circuit includes a reverse noise generating circuit having a first input terminal coupled to a first pulse terminal or a second pulse terminal of the primary switch, a second input terminal configured to receive an adjusting signal, and an output terminal configured to provide a noise control signal. The secondary winding has a first terminal and a second terminal. The noise control signal is coupled to either terminal of the secondary winding of the transformer.

Abstract: A method for controlling a voltage converter includes the following steps. A feedback compensation signal is generated based on an output voltage of the voltage converter. An output representation signal is compared with a first threshold and a second threshold. A switch control signal to control the turn-on and turn-off of a power circuit of the voltage converter is adjusted based on an ultra-light load feedback value when the output representation signal is less than the first power threshold. The switch control signal is adjusted based on the feedback compensation signal when the output representation signal is greater than the first power threshold. The second threshold is greater than the first threshold, and the ultra-light load feedback value is greater than the feedback compensation signal when the output representation signal is equal to the second threshold.

Abstract: A control circuit for a voltage regulator has an energy regulation circuit and a switching control circuit. The energy regulation circuit provides a regulation signal based on an output voltage, an output current, and a maximum energy reference. The maximum energy reference decreases with increasing of an ambient temperature and increases with decreasing of the ambient temperature. The switching control circuit provides a switching control signal based on the regulation signal to turn ON and turn OFF at least one switch of a plurality of switches of the voltage regulator, such that the output voltage and the output current satisfy a first relationship when the ambient temperature equals a first temperature value, and the output voltage and the output current satisfy a second relationship when the ambient temperature equals a second temperature value.

Abstract: A control circuit for a DC-DC converter has an over-current comparison circuit, an adaptive voltage position (AVP) control circuit and a switching control circuit. The over-current comparison circuit provides an over-current comparison signal by comparing an output current with a current limit value. The AVP control circuit provides a position signal based on a voltage identification code, an output voltage, an output current and the over-current comparison signal. The switching control circuit controls the DC-DC converter based on the position signal. When the output current is smaller than the current limit value, the output voltage varies along a first voltage position curve, and otherwise, the output voltage varies along a second voltage position curve.

Abstract: A control circuit for a DC-DC converter has an adaptive voltage position (AVP) control circuit and a switching control circuit. The AVP control circuit generates a position signal based on an output voltage, an output current, a voltage identification code and a set of adaptive voltage control commands. The switching control circuit generates a switching control signal based on the position signal to control the DC-DC converter. When the output current is smaller than a current threshold, the control circuit chooses one of a first voltage position curve and a second voltage position curve as a load line according to the set of adaptive voltage control commands, and when the output current is larger than the current threshold, the control circuit chooses the remaining voltage position curve as the load line according to the set of adaptive voltage control commands.

Abstract: A power chip with a switching converter, having: a power pin configured to receive an input voltage, an indicating signal generating circuit configured to generate an indicating signal; a communicating circuit configured to receive/transmit communication data; and a multi-function pin configured to receive/transmit communication data and/or to provide the indicating signal under certain conditions.

Abstract: A DCR current sensing circuit used in a switching converter having a power switch and an inductor. The DCR current sensing circuit has a current sensing capacitor coupled in series with a current sensing resistor to form a RC circuit, a current mirror, a first and a second compensation circuits, wherein the RC circuit is coupled in parallel with the inductor. The current mirror generates a first mirror current signal and a second mirror current signal based on a voltage across the current sensing capacitor. The first compensation circuit receives the first mirror current signal and generates a first current sensing signal for meeting a first requirement of the switching converter. The second compensation circuit receives the second mirror current signal and generates a second current sensing signal for meeting a second requirement of the switching converter.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A totem pole PFC (Power Factor Correction) circuit, having: a first switch, a second switch and a control circuit. When the totem pole PFC circuit works in CCM (Continuous Current Mode), the control circuit is configured to turn on a main switch when a current detecting signal indicative of an AC input current of the totem pole PFC circuit decreases to a current valley reference signal, and keep the main switch ON for a first on-time period. When the totem pole PFC circuit works in DCM (Discontinuous Current Mode), the control circuit is configured to turn on the main switch at a valley of a switching voltage after expiry of a time delay started from when the AC input current decreases to zero, and keep the main switch ON for a second on-time period.

Abstract: A power converter includes a controller for driving a corresponding power switch in the power converter. The controller may have a current sense terminal adapted to sense/receive a current sense signal indicative of a current flowing through the corresponding power switch and a current limit terminal adapted to receive a reference current sense signal indicative of a current flowing through another power switch in the power converter. The controller may turn off the corresponding power switch once the current sense signal reaches a peak value of the reference current sense signal.

Abstract: A charge pump comprises two bridge arms coupled in parallel, two capacitors, and a control circuit. Each bridge arm has two pairs of switches coupled in series, each pair of switches having two switches coupled in series through a common node. Each capacitor is connected between the two common nodes of the corresponding bridge arm. The control circuit provides a mode signal by comparing an output voltage of the charge pump with two threshold voltages via a hysteretic comparison, and provides two control signals with opposite logic states based on the mode signal to control each pair of the switches to work complementarily, wherein the logic states of the control signals flip in response to transiting from a first status to a second status of the mode signal, and maintain in response to transiting from the second status to the first status of the mode signal.

Abstract: A method for controlling a switching mode power supply is disclosed. An auxiliary winding feedback voltage of the switching mode power supply is sampled and held to obtain an auxiliary winding sample hold voltage. The auxiliary winding feedback voltage is sampled and held at an inflection point time to obtain an auxiliary winding inflection point voltage when the switching mode power supply operates in DCM or CRM. A secondary rectifier forward voltage signal is generated based on the auxiliary winding sample hold voltage and the auxiliary winding inflection point voltage before the switching mode power supply operates in CCM. A correction voltage is provided based on the secondary rectifier forward voltage signal when the switching power supply operates in CCM. An error amplifier signal is generated based on the correction voltage. The output power of the switching mode power supply is adjusted based on the error amplifier signal.

Abstract: A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.