Abstract: The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, the memory controller comprising: a central buffer coupled to the host controller via a command/address bus to receive a command/address signal from the host controller, wherein the central buffer is configured to determine whether the command/address signal conforms to an authority management rule and configure a buffer control command based on the determination result, so that the buffer control command indicates whether to restrict access of the host controller to the memory module; and a data buffer coupled via a data buffer command channel to the central buffer to receive the buffer control command, wherein the data buffer is configured to selectively restrict access of the host controller to the memory module based on the buffer control command; wherein the buffer control command comprises a plurality of time-sequenced fields, and the central

Abstract: This application relates to the field of memory technology, in particular to a method and a system for remapping a row address on a multichannel DIMM. The method is applied to a memory controller, comprising: receiving a first read/write access address and extracting a first channel row address from the first read/write access address; encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range; forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. The present application can alleviate side channel attack without causing degradation of read/write performance.

Abstract: A data compression method includes: storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address of the memory module, and identifying the compressed data by using redundant ECC bits to form first identification information.

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: The application discloses a device and a method for picking up top k values from N values. The method comprises: A) controlling a buffer to receive values into a data pool until the number of values in the data pool reaches the predetermined memory size; B) dividing the values in the data pool into a first portion and a second portion; C) discarding the values in the second portion and controlling the buffer to continue to receive values into the data pool; D) repeating steps B to C until the buffer has received all the N values; E) dividing the values in the data pool into the first portion and the second portion until the number of values in the first portion reaches k; and F) controlling the buffer to output the k values in the first portion as the top k values.

Abstract: A multi-processing accelerating method and a multi-processing accelerating system based on an electronic-system-level virtual platform are provided. The method includes: creating a controller domain and a plurality of client domains on the electronic-system-level virtual platform, each client domain corresponds to a process; and controlling, by the controller domain, the client domains in parallel to enable multi-processing for the client domains. The multi-processing accelerating method and the system for the electronic-system-level virtual platform can effectively accelerate the operation of the electronic-system-level virtual platform and improve the efficiency of software development of the electronic-system-level virtual platform.

Abstract: The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.

Abstract: An AI computing platform, an AI computing method, and an AI cloud computing system, the platform including: at least one computing component, each computing component includes: a processor, configured to initiate a calculation task and decompose the calculation task into a plurality of ordered subtasks according to a network topology information table stored therein; a plurality of near-memory computing modules, the plurality of near-memory computing modules connecting in pairs with the processor, and the plurality of near-memory computing modules connecting in pairs with each other, wherein the plurality of near-memory computing modules are each configured to implement different operation types, and the plurality of near-memory computing modules complete one or more of the plurality of subtasks according to the operation types they each implement.

Abstract: A method for splitting operators, a device for splitting operators and a non-transitory computer readable storage medium are provided. The method includes: S1: obtaining buffer information required by target operators; and S2: splitting the target operators to obtain a splitting result of the target operators, and obtaining a storage layout of the target operators in the first memory, based on the buffer information required by the target operators and a storage capacity of the first memory; the splitting result of the target operators and the storage layout of the target operators are used to implement a mapping of a target artificial intelligence model to an artificial intelligence hardware accelerator.

Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

Abstract: The application discloses a data encryption and decryption system and method. The system includes a host system, a sequencer, a hardware processor, multiple direct memory access modules, and multiple cryptography engines, the cryptography engine comprises an input buffer, an output buffer, a symmetric encryption/decryption algorithm module and a digest algorithm module. The host system determines encryption/decryption calculation method and/or digest calculation method, and generates corresponding encryption/decryption calculation commands and/or digest calculation commands. The sequencer analyzes the encryption/decryption calculation commands and/or digest calculation command to generate control flow commands, and controls one or more of the multiple direct memory access modules via the control flow commands to input data to be encrypted/decrypted into the input buffer of one or more cryptography engines.

Abstract: The present application discloses a detection structure for chip edge cracks and a detection method thereof. In one embodiment, the detection structure comprises a test ring located between a chip scribe line and a sealing ring, wherein the chip internally comprises two test pads for detecting continuity of the test ring, the sealing ring comprises a P-type doped ring located in a substrate and a shallow trench isolation area for isolating the sealing ring the test ring, the shallow trench isolation area is formed with N-type doped regions electrically connected to the two test pads respectively; the test ring comprises a multi-layer interconnection structure located on the substrate and the interconnection structure is electrically connected to the two test pads through the N-type doped regions. The present application can detect edge cracks caused by wafer manufacturing, die sawing, and chip packaging processes to reduce reliability risk.

Abstract: A data processing method and an acceleration unit are provided. The method includes: S11, reading a row of a target matrix as a target row; S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset, and writing each element in the shifted target row into a corresponding row buffer respectively; S13, reading a next row of the target row from the target matrix as a new target row, if the next row of the target row is not the last row of the target matrix and an available storage space exists in the row buffers; S14, reading corresponding elements from each row buffer according to a preset rule, and writing the elements read from each row buffer into an output buffer as a row, step S14 is repeated until all elements in all row buffers are written into the output buffer.

Abstract: An electrostatic discharge and electrical overstress detection circuit includes protection circuit, sensing circuit, clamp circuit, several stages of sampling logic circuits connected in sequence and storage circuit. Protection circuit is coupled between input/output pin and internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen. Sensing circuit and clamp circuit are coupled between power supply terminal and ground terminal. Each stage of sampling logic circuit is coupled to power supply terminal and memory cell of storage circuit, and the first stage of sampling logic is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cell.

Abstract: A computing system includes a host computing device and a slave computing device. The host computing device comprises a host processor, a host device memory and a host address mapping management. The host address mapping management manages a system memory page table, and converts, in response to a data access request from a processing process run on the host processor, requested virtual addresses into host device physical addresses based on the system memory page table to allow the processing process to access corresponding host storage units. The slave computing device includes a slave processor callable by the host processor to assist the host processor in running the processing processes, a slave device memory and a slave address mapping management unit.

Abstract: The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.

Abstract: A topology of accelerators is provided, including a plurality of accelerators and a broadcast buffer. Each of the plurality of accelerators corresponds to a first memory and obtain input data from an external second memory respectively, wherein the accelerator can only directly access its corresponding first memory, and the broadcast buffer is coupled between one of the plurality of accelerators and the corresponding first memory. When receiving a write command and the input data from the accelerator to which it is coupled, the broadcast buffer is configured to write the input data into the corresponding first memory according to the write command, and when broadcast is enabled, the broadcast buffer is configured to broadcast the write command and the weight data in the input data. This application can improve the access performance of the accelerators and reduce the access delay.

Abstract: The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

Abstract: The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

Abstract: Self-cooling semiconductor resistor and manufacturing method thereof are provided. The resistor comprises: multiple N-type and P-type wells in a semiconductor substrate, first polysilicon gates on each N-type well, second polysilicon gates on each P-type well, and metal interconnect layers. The multiple N-type and P-type wells are arranged alternately in row and column direction, respectively. N-type and P-type deep doped regions are formed on each N-type and P-type well, respectively. The first and second polysilicon gates are N-type and P-type deep doped respectively, and there is no gate oxide layer between the first and second polysilicon gates and the semiconductor substrate. The metal interconnect layers connect the multiple first and second polysilicon gates as an S-shaped structure. In the present application, the flow direction of heat is from the inside of the resistor to its surface, thereby realizing heat dissipation and cooling.