Patents Assigned to Mosaid Technologies, Inc.
  • Patent number: 11049574
    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 29, 2021
    Assignee: Mosaid Technologies Inc.
    Inventors: Jin-Ki Kim, Peter B. Gillingham
  • Publication number: 20130332055
    Abstract: A method and apparatus for starting an internal combustion engine is disclosed. A motor is mechanically coupled to the engine, the engine having at least one moveable element mounted in a chamber, the moveable element being operable to cause a changing compression condition within the chamber and being mechanically coupled to a shaft for generating mechanical power. The method involves causing the motor to supply a positioning torque to the engine to move the at least one moveable element into a starting position. The method also involves causing the motor to supply a starting torque to the engine when the at least one moveable element is in the starting position to cause the moveable element to accelerate from the starting position under low compression conditions to generate sufficient momentum to overcome a peak compression condition in the chamber, thereby reducing the starting torque required to start the engine.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 12, 2013
    Applicant: Mosaid Technologies Inc.
    Inventors: Nicolas Bouchon, Martin Strange
  • Publication number: 20130234787
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: MOSAID Technologies, Inc.
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Publication number: 20130215798
    Abstract: A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services.
    Type: Application
    Filed: December 3, 2012
    Publication date: August 22, 2013
    Applicant: MOSAID Technologies Inc.
    Inventor: MOSAID Technologies, Inc.
  • Patent number: 8474429
    Abstract: A method and apparatus for starting an internal combustion engine is disclosed. A motor is mechanically coupled to the engine, the engine having at least one moveable element mounted in a chamber, the moveable element being operable to cause a changing compression condition within the chamber and being mechanically coupled to a shaft for generating mechanical power. The method involves causing the motor to supply a positioning torque to the engine to move the at least one moveable element into a starting position, The method also involves causing the motor to supply a starting torque to the engine when the at least one moveable element is in the starting position to cause the moveable element to accelerate from the starting position under low compression conditions to generate sufficient momentum to overcome a peak compression condition in the chamber, thereby reducing the starting torque required to start the engine.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: July 2, 2013
    Assignee: Mosaid Technologies Inc.
    Inventors: Nicolas Bouchon, Martin Strange
  • Patent number: 8295185
    Abstract: An addressable outlet for use as part of local area network based on wiring installed in a building, such as telephone, electrical, cable television, dedicated wiring, and the like. The use of such wiring for data communications networks in addition to the wiring's primary usage creates a need for ways of determining the condition of the network and monitoring this information remotely. Network condition includes such factors as continuity of wiring, connector status, connected devices, topology, signal delays, latencies, and routing patterns. Providing basic processing and addressing capabilities within the outlet permits messaging to and from specific individual outlets, thereby allowing inquiries and reports of the condition of the immediate environment of each outlet. In addition, outlets can be configured with sensors to report on voltage, temperature, and other measurable quantities.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: October 23, 2012
    Assignee: Mosaid Technologies Inc.
    Inventor: Yehuda Binder
  • Patent number: 8023519
    Abstract: A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: September 20, 2011
    Assignee: Mosaid Technologies, Inc.
    Inventors: David A. Brown, Peter B. Gillingham
  • Patent number: 7830877
    Abstract: Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: November 9, 2010
    Assignee: Mosaid Technologies Inc.
    Inventor: David A. Brown
  • Publication number: 20100128546
    Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
    Type: Application
    Filed: September 18, 2009
    Publication date: May 27, 2010
    Applicant: Mosaid Technologies, Inc.
    Inventor: Richard C. Foss
  • Patent number: 7656988
    Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 2, 2010
    Assignee: MOSAID Technologies, Inc.
    Inventor: Tony Mai
  • Patent number: 7633960
    Abstract: A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: December 15, 2009
    Assignee: Mosaid Technologies Inc.
    Inventors: David A. Brown, Peter B. Gillingham
  • Patent number: 7616035
    Abstract: A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: November 10, 2009
    Assignee: MOSAID Technologies, Inc.
    Inventor: Dieter Haerle
  • Patent number: 7609573
    Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 27, 2009
    Assignee: MOSAID Technologies, Inc.
    Inventor: Richard C. Foss
  • Patent number: 7599246
    Abstract: A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: October 6, 2009
    Assignee: MOSAID Technologies, Inc.
    Inventors: Richard C. Foss, Peter B. Gillingham, Graham Allan
  • Patent number: 7551492
    Abstract: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: June 23, 2009
    Assignee: Mosaid Technologies, Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 7535749
    Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 19, 2009
    Assignee: Mosaid Technologies, Inc.
    Inventor: Valerie L. Lines
  • Publication number: 20090121760
    Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 14, 2009
    Applicant: MOSAID Technologies, Inc.
    Inventor: Dieter Haerle
  • Patent number: 7532050
    Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 12, 2009
    Assignee: MOSAID Technologies, Inc.
    Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
  • Publication number: 20090086876
    Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.
    Type: Application
    Filed: December 2, 2008
    Publication date: April 2, 2009
    Applicant: MOSAID Technologies, Inc.
    Inventor: Tony Mai
  • Publication number: 20090073792
    Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
    Type: Application
    Filed: July 31, 2008
    Publication date: March 19, 2009
    Applicant: Mosaid Technologies, Inc.
    Inventor: Richard C. Foss