Patents Assigned to Mosaid Technologies, Inc.
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Patent number: 7003625Abstract: A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the entity to distribute the entities among the columns to maximize memory utilization. A match for a search key stored in one of the plurality of columns can be found in a single search operation.Type: GrantFiled: March 10, 2003Date of Patent: February 21, 2006Assignee: Mosaid Technologies, Inc.Inventor: Lawrence King
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Patent number: 7002824Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.Type: GrantFiled: August 5, 2004Date of Patent: February 21, 2006Assignee: Mosaid Technologies, Inc.Inventors: Robert N. McKenzie, Dieter Haerle, Sean Lord
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Patent number: 6990552Abstract: Method and apparatus using a Content Addressable Memory for sorting a plurality of data items is presented. The data items to be sorted are stored in the Content Addressable Memory. A plurality of bit-by-bit burst searches are performed on the contents of the Content Addressable Memory with all other bits in the search key masked. The number of burst searches is proportional to the total number of bits in the data items to be sorted. The search is deterministic dependent on the number of bits in each data item on which a sort is performed and on the number of data items to be sorted.Type: GrantFiled: October 31, 2002Date of Patent: January 24, 2006Assignee: Mosaid Technologies, Inc.Inventor: Mourad Abdat
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Patent number: 6980448Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.Type: GrantFiled: June 17, 2003Date of Patent: December 27, 2005Assignee: MOSAID Technologies, Inc.Inventors: Richard C. Foss, Peter B. Gillingham, Robert F. Harland, Valerie L. Lines
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Publication number: 20050265506Abstract: A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.Type: ApplicationFiled: August 1, 2005Publication date: December 1, 2005Applicant: Mosaid Technologies, Inc.Inventors: Richard Foss, Peter Gillingham, Graham Allan
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Patent number: 6959346Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes.Type: GrantFiled: December 22, 2000Date of Patent: October 25, 2005Assignee: MOSAID Technologies, Inc.Inventors: Arthur John Low, Stephen J. Davis
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Publication number: 20050175005Abstract: A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.Type: ApplicationFiled: April 6, 2005Publication date: August 11, 2005Applicant: MOSAID Technologies, Inc.Inventor: David Brown
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Publication number: 20050162200Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: ApplicationFiled: December 10, 2004Publication date: July 28, 2005Applicant: Mosaid Technologies, Inc.Inventor: Dieter Haerle
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Patent number: 6917954Abstract: A load balancing mechanism maps a binary tree representation of a routing table into a set of fixed size memories. The mechanism efficiently utilizes the memory in the routing table without violating the tree precedence constraints and the memory access requirements of a pipelined system. The mechanism stores a subtree associated with a densely populated level of the binary tree in memory associated with lower levels.Type: GrantFiled: April 24, 2002Date of Patent: July 12, 2005Assignee: Mosaid Technologies, Inc.Inventors: Imtiaz Ahmad, David A. Brown
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Publication number: 20050147113Abstract: A number of hash tables are accessed concurrently with a different computed index based on a single search key for each hash table. Each index identifies a location in one of the hash tables capable of storing at least one entry. If all indexed locations are used, the entries stored in the lookup table can be reordered so that the new entry can be inserted in one of the locations identified by the computed indexes.Type: ApplicationFiled: February 28, 2005Publication date: July 7, 2005Applicant: MOSAID Technologies, Inc.Inventor: David Brown
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Patent number: 6879271Abstract: We present a method and apparatus for performing adaptive data compression. An alphabet and vocabulary in the encoder and decoder is built adaptively and stored in a dictionary as symbols are to be encoded and decoded. Each time an unknown symbol is to be encoded by the encoder, the encoder adds the symbol to the dictionary and transmits it in plain in the encoded string. The code words transmitted by the encoder include symbols and indexes. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. The decoder examines the prefix bit of each code word as it is received to determine if the code word stores a symbol in plain or in index. If the code word stores a symbol in plain, the decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary.Type: GrantFiled: February 27, 2004Date of Patent: April 12, 2005Assignee: MOSAID Technologies, Inc.Inventor: Mourad Abdat
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Patent number: 6880064Abstract: A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.Type: GrantFiled: June 21, 2001Date of Patent: April 12, 2005Assignee: MOSAID Technologies, Inc.Inventor: David A. Brown
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Publication number: 20050068839Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.Type: ApplicationFiled: August 5, 2004Publication date: March 31, 2005Applicant: MOSAID Technologies, Inc.Inventors: Robert McKenzie, Dieter Haerle, Sean Lord
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Patent number: 6862287Abstract: A number of hash tables are accessed concurrently with a different computed index based on a single search key for each hash table. Each index identifies a location in one of the hash tables capable of storing at least one entry. If all indexed locations are used, the entries stored in the lookup table can be reordered so that the new entry can be inserted in one of the locations identified by the computed indexes.Type: GrantFiled: June 28, 2002Date of Patent: March 1, 2005Assignee: MOSAID Technologies, Inc.Inventor: David A. Brown
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Patent number: 6856595Abstract: A switch applies back pressure to an ingress port while an output queue is congested. The switch includes an output queue associated with an egress port in the switch. The output queue stores packet pointers to data to be transmitted to the egress port. A back pressure controller in the switch applies back pressure to an ingress port while the output queue is congested upon receiving data at the ingress port to be transmitted to the egress port.Type: GrantFiled: May 19, 2000Date of Patent: February 15, 2005Assignee: MOSAID Technologies, Inc.Inventor: David A. Brown
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Publication number: 20050030208Abstract: We present a method and apparatus for performing adaptive data compression. An alphabet and vocabulary in the encoder and decoder is built adaptively and stored in a dictionary as symbols are to be encoded and decoded. Each time an unknown symbol is to be encoded by the encoder, the encoder adds the symbol to the dictionary and transmits it in plain in the encoded string. The code words transmitted by the encoder include symbols and indexes. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. The decoder examines the prefix bit of each code word as it is received to determine if the code word stores a symbol in plain or in index. If the code word stores a symbol in plain, the decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary.Type: ApplicationFiled: February 27, 2004Publication date: February 10, 2005Applicant: MOSAID Technologies, Inc.Inventor: Mourad Abdat
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Publication number: 20050030948Abstract: In a switch with multiple physical links to a destination, data is forwarded to the destination by distributing received data across the physical links. A flow hash is selected for the received data's data flow dependent on a destination address and source address included in the received data. The flow hash selects one of the physical links to the destination for a data flow but potentially a different physical link for a different data flow, thereby forwarding the received data by distributing the received data across the physical links while maintaining frame ordering within a data flow.Type: ApplicationFiled: June 29, 2004Publication date: February 10, 2005Applicant: MOSAID Technologies, Inc.Inventor: Richard Wyatt
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Patent number: 6839825Abstract: A method and apparatus for minimizing memory required for storing non-binary width data structures is disclosed. The non-binary width data structure is segmented into plural segments. The segments are stored in a plurality of memory blocks. Mapper logic maps a logical address to a physical address in the memory blocks to access non-binary width entries in the non-binary width data structure stored in the memory blocks.Type: GrantFiled: June 21, 2001Date of Patent: January 4, 2005Assignee: Mosaid Technologies, Inc.Inventor: David A. Brown
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Publication number: 20040264621Abstract: An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.Type: ApplicationFiled: August 25, 2003Publication date: December 30, 2004Applicant: MOSAID Technologies, Inc.Inventor: Tony Mai
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Patent number: 6836771Abstract: We present a lookup table which allows sparse subtree descriptors and dense subtree descriptors to be stored in the same memory. A subtree entry in the memory stores a dense subtree descriptor for a dense subtree or a plurality of sparse subtree descriptors for sparse subtrees. The subtree entry is indexed by a leaf in the previous subtree. The sparse subtree descriptor stores at least one node descriptor. The node descriptor describes a set of leaves in the sparse subtree having a common value. The common value is encoded in the node descriptor using run length encoding.Type: GrantFiled: January 2, 2003Date of Patent: December 28, 2004Assignee: MOSAID Technologies, Inc.Inventor: David A. Brown