Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.

Abstract: A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.

Abstract: A clock feeding circuit to a semiconductor memory wherein the memory is comprised of separate independent control circuits each requiring a clock signal, comprising apparatus for receiving a control signal applied to one of the control circuits, and apparatus for applying a clock signal to the one of the independent control circuits, restricted to the one of the independent control circuits.

Abstract: A digital signal scrambler for use in testing semiconductor memory circuits such as RAMs. The scrambler is comprised of look-up tables in conjunction with EXCLUSIVE OR logic circuitry, for receiving generated address and data signals and transmitting scrambled signals in response thereto, conforming to the predefined topological scrambling function of the memory circuit being tested. The digital signal scrambler of the present invention is of simple and inexpensive design, is easy to use and typically occupies very little circuit board area.