Patents Assigned to Mosaid Technologies Incorporated
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Patent number: 11948629Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: February 14, 2023Date of Patent: April 2, 2024Assignee: Mosaid Technologies IncorporatedInventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Patent number: 11880569Abstract: A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.Type: GrantFiled: April 19, 2023Date of Patent: January 23, 2024Assignee: Mosaid Technologies IncorporatedInventors: Peter B. Gillingham, Graham Allan
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Patent number: 11721761Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.Type: GrantFiled: January 27, 2022Date of Patent: August 8, 2023Assignee: Mosaid Technologies IncorporatedInventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
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Patent number: 11669248Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.Type: GrantFiled: April 28, 2022Date of Patent: June 6, 2023Assignee: Mosaid Technologies IncorporatedInventors: Peter B. Gillingham, Graham Allan
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Patent number: 11664463Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.Type: GrantFiled: July 7, 2021Date of Patent: May 30, 2023Assignee: Mosaid Technologies IncorporatedInventor: Hyoung Seub Rhie
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Patent number: 11600323Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: April 30, 2021Date of Patent: March 7, 2023Assignee: Mosaid Technologies IncorporatedInventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Patent number: 11362645Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each power island of the plurality of power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: GrantFiled: July 14, 2020Date of Patent: June 14, 2022Assignee: Mosaid Technologies IncorporatedInventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
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Patent number: 11347396Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.Type: GrantFiled: November 17, 2020Date of Patent: May 31, 2022Assignee: Mosaid Technologies IncorporatedInventors: Peter B. Gillingham, Graham Allan
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Patent number: 11150808Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: GrantFiled: June 3, 2020Date of Patent: October 19, 2021Assignee: Mosaid Technologies IncorporatedInventor: Jin-Ki Kim
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Patent number: 11102809Abstract: In one embodiment, a method is performed by a wireless station. The method includes determining that a wireless network provides relay service. The wireless network includes an access point and one or more relay nodes. The method further includes transmitting a relay-service desirability indication to the access point. The method also includes receiving a relay-service confirmation from the access point. The wireless station is operable to transmit at a first station-transmission power level during a first time period and a second station-transmission power level during a second time period. The second station-transmission power level is a reduced station-transmission power level as compared to the first station-transmission power level. In addition, the method includes transmitting an uplink transmission at the second station-transmission power level responsive to the relay-service confirmation from the access point.Type: GrantFiled: January 24, 2020Date of Patent: August 24, 2021Assignee: Mosaid Technologies IncorporatedInventors: Xuejun Lu, Hanwu Hu
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Patent number: 11088289Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.Type: GrantFiled: March 12, 2020Date of Patent: August 10, 2021Assignee: Mosaid Technologies IncorporatedInventor: Hyoung Seub Rhie
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Patent number: 11082956Abstract: In one embodiment, a method is performed by a base station in a wireless network. The method includes receiving from a user device a request to reconfigure already-active uplink semi-persistent scheduling (SPS). The already-active uplink SPS grants the user device a resource block allocation (RBA) and a modulation and coding scheme (MCS) for periodic uplink transmissions. The already-active uplink SPS includes a time-interval parameter, the time-interval parameter specifying a time interval between the periodic uplink transmissions. The request includes information related to a proposed adjustment of the time-interval parameter. The method further includes reconfiguring the already-active uplink SPS. The reconfiguring includes modifying the time-interval parameter based, at least in part, on the information.Type: GrantFiled: March 18, 2020Date of Patent: August 3, 2021Assignee: Mosaid Technologies IncorporatedInventor: Khiem Le
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Publication number: 20150092494Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: Mosaid Technologies IncorporatedInventor: Hyoung Seub Rhie
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Publication number: 20140307508Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.Type: ApplicationFiled: October 4, 2013Publication date: October 16, 2014Applicant: MOSAID Technologies IncorporatedInventor: Hyoung Seub Rhie
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Publication number: 20140269087Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Hyoung Seub Rhie
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Patent number: 8825966Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.Type: GrantFiled: February 2, 2012Date of Patent: September 2, 2014Assignee: MOSAID Technologies IncorporatedInventor: Peter Gillingham
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Patent number: 8819377Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.Type: GrantFiled: March 2, 2011Date of Patent: August 26, 2014Assignee: MOSAID Technologies IncorporatedInventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20140219664Abstract: An optical communication system and method of use are described. The system comprises an optical source adapted to receive a digitally encoded data signal comprising sequences of data at a data rate (B) and comprising two signal levels representing a first state and a second state of the data signal, the optical source being adapted to produce an optical signal substantially frequency modulated with frequency excursion ?? comprising a first instantaneous frequency (?0) associated to the first state and a second instantaneous frequency (?1) associated to the second state; an optical converter adapted to receive the substantially frequency modulated optical signal, the optical converter having an optical transfer function varying with frequency and including at least one pass band, the at least one pass band having a peak transmittance and at least a low-transmittance region.Type: ApplicationFiled: July 25, 2013Publication date: August 7, 2014Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Marco ROMAGNOLI, Paola GALLI
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Patent number: RE48766Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.Type: GrantFiled: December 4, 2019Date of Patent: October 5, 2021Assignee: Mosaid Technologies IncorporatedInventor: Hyoung Seub Rhie
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Patent number: RE49018Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: GrantFiled: May 9, 2019Date of Patent: April 5, 2022Assignee: Mosaid Technologies IncorporatedInventor: Dieter Haerle