Patents Assigned to Mosaid Technologies Incorporated
  • Patent number: 11150808
    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: October 19, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 11102809
    Abstract: In one embodiment, a method is performed by a wireless station. The method includes determining that a wireless network provides relay service. The wireless network includes an access point and one or more relay nodes. The method further includes transmitting a relay-service desirability indication to the access point. The method also includes receiving a relay-service confirmation from the access point. The wireless station is operable to transmit at a first station-transmission power level during a first time period and a second station-transmission power level during a second time period. The second station-transmission power level is a reduced station-transmission power level as compared to the first station-transmission power level. In addition, the method includes transmitting an uplink transmission at the second station-transmission power level responsive to the relay-service confirmation from the access point.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 24, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventors: Xuejun Lu, Hanwu Hu
  • Patent number: 11088289
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 10, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Patent number: 11082956
    Abstract: In one embodiment, a method is performed by a base station in a wireless network. The method includes receiving from a user device a request to reconfigure already-active uplink semi-persistent scheduling (SPS). The already-active uplink SPS grants the user device a resource block allocation (RBA) and a modulation and coding scheme (MCS) for periodic uplink transmissions. The already-active uplink SPS includes a time-interval parameter, the time-interval parameter specifying a time interval between the periodic uplink transmissions. The request includes information related to a proposed adjustment of the time-interval parameter. The method further includes reconfiguring the already-active uplink SPS. The reconfiguring includes modifying the time-interval parameter based, at least in part, on the information.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Khiem Le
  • Publication number: 20150092494
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Publication number: 20140307508
    Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
    Type: Application
    Filed: October 4, 2013
    Publication date: October 16, 2014
    Applicant: MOSAID Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Publication number: 20140269087
    Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Hyoung Seub Rhie
  • Patent number: 8825966
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 2, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: Peter Gillingham
  • Patent number: 8819377
    Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: August 26, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Publication number: 20140219664
    Abstract: An optical communication system and method of use are described. The system comprises an optical source adapted to receive a digitally encoded data signal comprising sequences of data at a data rate (B) and comprising two signal levels representing a first state and a second state of the data signal, the optical source being adapted to produce an optical signal substantially frequency modulated with frequency excursion ?? comprising a first instantaneous frequency (?0) associated to the first state and a second instantaneous frequency (?1) associated to the second state; an optical converter adapted to receive the substantially frequency modulated optical signal, the optical converter having an optical transfer function varying with frequency and including at least one pass band, the at least one pass band having a peak transmittance and at least a low-transmittance region.
    Type: Application
    Filed: July 25, 2013
    Publication date: August 7, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Marco ROMAGNOLI, Paola GALLI
  • Publication number: 20140192593
    Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Jin-Ki KIM
  • Publication number: 20140192596
    Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.
    Type: Application
    Filed: March 14, 2013
    Publication date: July 10, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Hyoung Seub RHIE
  • Publication number: 20140195715
    Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
    Type: Application
    Filed: February 5, 2014
    Publication date: July 10, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Jin-Ki KIM, HakJune OH, Hong Beom PYEON, Steven PRZYBYLSKI
  • Publication number: 20140185379
    Abstract: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.
    Type: Application
    Filed: March 5, 2014
    Publication date: July 3, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Jin-Ki KIM
  • Publication number: 20140179059
    Abstract: An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicant: MOSAID Technologies Incorporated
    Inventor: Hong Beom PYEON
  • Publication number: 20140170902
    Abstract: In conjunction with a wiring in a house carrying data network signal, a modular outlet includes a base module and interface module. The base module connects to the wiring and is attached to the surface of a building. The interface module provides a data unit connection. The interface module is mechanically attached to the base module and electrically connected thereto. The wiring may also carry basic service signal such as telephone, electrical power and cable television (CATV). In such a case, the outlet provides the relevant connectivity either as part of the base module or as part of the interface module. Both proprietary and industry standard interfaces can be used to interconnect the module. Furthermore, a standard computer expansion card (such as PCI, PCMCIA and alike) may be used as interface module.
    Type: Application
    Filed: November 19, 2013
    Publication date: June 19, 2014
    Applicant: MOSAID Technologies Incorporated
    Inventor: Yehuda BINDER
  • Publication number: 20140173322
    Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Hong Beom PYEON, HakJune OH
  • Publication number: 20140153582
    Abstract: The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: MOSAID Technologies Incorporated
    Inventor: David E. JONES
  • Publication number: 20140151774
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 5, 2014
    Applicant: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Patent number: RE48766
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 5, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie