Abstract: An improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.

Abstract: An improved method for reworking photoresist is provided for decreasing cycle time of photoresist reworking process. A semiconductor substrate with an underlying layer is provided for patterning. A photoresist pattern is formed on the underlying layer. A photoresist reworking process is performed after an after-development-inspection (ADI) is performed. The photoresist reworking method comprises the following steps. The semiconductor substrate is placed in organic stripper for removing the most portion of the photoresist pattern. Subsequently, the semiconductor substrate is placed in a single-wafer processor and an UV/O3 dry ashing is then performed to remove completely the residual photoresist pattern on the underlying layer. A new photoresist layer is deposited on the underlying layer after the photoresist pattern removed completely.

Abstract: A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter.

Abstract: A method of fabricating an oxide/nitride multilayer structure is disclosed. The multilayer structure of dielectric films could be applied for manufacturing E2PROM, flash memories, or the dielectric layers of a DRAM capacitor. In accordance with the present invention, all films are formed in the same chamber, and only one heating and one cooling step are needed to form an oxide/nitride/oxide structure or an oxide/nitride/oxide/nitride structure.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: A low power consumption delay locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase detector to the slow operating condition of the programmable delay. In a particular embodiment, this may be effectuated by incorporating at least one additional flip-flop section in the phase detector circuit and more than one such section may be utilized depending on the operating targets of maximum frequency and frequency range. By latching the phase detector outputs through the use of a fast/slow latch circuit, a minimum control pulse is defined which allows a unitized change on the voltage signals that control the programmable delay in a voltage controlled delay line. This also improves efficiency and reduces power consumption by eliminating switching current through transistors that control the voltage levels determining the programmable delay.

Abstract: A method for evaluating ratios of metallic impurities in lithographic materials is disclosed. The method comprises: separating said metal from said lithographic material by microwave heating; then adding said metal to an acid to form a solution; and finally analyzing said solution by a instrument to measure ratio of said metal.

Abstract: A method for producing identifying elements for identifying the specification of a MASK ROM, which can easily accompany the standard process of MASK ROM. Also disclosed a method for identifying a MASK ROM, which can identify the code specification of the MASK ROM produced using simple electrical tests before the product is delivered, thereby achieving high efficiency and low error rate.

Abstract: A method for protecting stepper alignment marks suitable for a substrate with an alignment mark on a scribe line and a metal layer that will be etched includes the following steps. First, a photoresist layer is formed over the metal layer. Next, a photo mask which has a predefined photo mask pattern for transfer to the metal layer is provided, and a pattern protecting the alignment marks is added to the photo mask pattern. Then, a photolithographic process is performed with the photo mask pattern on the photoresist layer to form the desired transferring photoresist mask to the metal layer and the protective photoresist mask for protecting the alignment marks.

Abstract: Disclosed is an apparatus and method for controlling boiling condition of hot H3PO4 solution by adjusting the vapor extracting rate thereof, wherein an acid tank filled with hot H3PO4 solution to a level surface is located in a treatment room and a temperature thermocouple is arranged above the level surface of the hot H3PO4 solution to monitor the vapor temperature near the level surface of the H3PO4 solution. The vapor temperature is used to adjust the extracting rate of the treatment room by control of a damper connected to an outlet of the treatment room. According to the present invention, the treatment apparatus and method can control the boiling condition of the hot H3PO4 solution thereof by properly adjusting the extracting rate, and therefore avoid defects and loss of control in manufacturing processes.

Abstract: A process for forming a gate oxide layer of a trench power MOSFET is provided. The process includes steps of providing a silicon substrate, forming a mask layer on the silicon substrate, removing a portion of the mask layer to expose a portion of the silicon substrate, removing the exposed portion of the silicon substrate to form the trench, removing remaining portion of the mask layer, forming a sacrificial oxide layer on the silicon substrate and on the bottom and sidewall of the trench by thermal oxidation under an operating temperature ranged from 1150 to 1300° C. and an operating time ranged from 20 to 60 minutes, removing the sacrificial oxide layer, and forming a gate oxide layer on the silicon substrate and on the bottom and sidewall of the trench.

Abstract: A method, and associated apparatus, for eliminating pulse width variations in digital delay lines. The method includes partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated, and the parasitic loading of the inverter between the blocks and the inverter on the output of the second block is the same. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks.

Abstract: A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Abstract: An integrated circuit memory device including at least one memory bank with the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided which are selectively couplable to the even and odd portions of the memory banks respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses.

Abstract: A wafer transfer method using a robot arm for sucking the front-side of the uppermost one of a plurality of wafers stored in a cassette, and for transferring the wafer having a tape adhered to the front-side thereof to a semiconductor tape-peeling device for tape-peeling. Although the wafer warps, the undesired effect that the robot arm crashes any of the wafers can be avoided by using this method.

Abstract: An inspection device for examining a piece of aperture graphite of an extraction electrode, and the aperture graphite includes a to-be-examined curve and a to-be-examined engagement portion. The inspection device includes a sidewall surface having a standard curve marked thereon, and an examination engagement portion having a predetermined positional relationship with the sidewall surface. After the to-be-examined engagement portion is engaged with the examination engagement portion, and after the to-be-examined curve is projected onto the sidewall surface, the suitability of the aperture graphite can be determined according to the amount of differences between the projected to-be-examined curve and the standard curve.

Abstract: In the invention, a photoresist layer is first spread on a semiconductor structure, and then using a photomask with a specially designed pattern exposes the photoresist layer. Next, the photoresist layer is developed to form a patterned photoresist layer. Thereafter, using the patterned photoresist layer as a mask, a trench is formed in the semiconductor structure by selective etching. The pattern of the photomask according to the invention is formed as in the following steps. At first, a first pattern extending in a first direction and having a first side and a second side that is opposite to the first side is formed. Next, a second pattern extending in a second direction that is perpendicular to the first direction is formed in such a way that an end of the second pattern is connected with the first side of the first pattern. Thereafter, a concave edge is formed on the second side to substantially face the second pattern.