Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally crosssectionally modified T-

Abstract: A pencil sharpener (10) is disclosed as including a body (12) with a hole (22) for receiving an end of a pencil, a cutting blade (24) secured to the body (12) for sharpening the pencil, and a stopper (30) movable relative to the body (12) to vary the length of the end of the pencil which may be received into the hole (22).

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract: A process of fabricating a shallow trench isolation structure includes the steps of: providing a substrate; forming a first insulating layer over the substrate; forming a nitride masking layer over the first insulating layer; patterning and etching the nitride masking layer, the first insulating layer and the substrate to remove portions of the nitride masking layer, the first insulating layer and the substrate thereby forming an exposed trench in the substrate, the trench substantially defining boundaries of the isolation structure; depositing a second insulating layer into the trench and over the nitride masking layer; planarizing the second insulating layer to expose the nitride masking layer; removing the nitride masking layer to expose the first insulating layer, and forming a divot proximate an edge of the trench; depositing a silicon layer into the divot, and over the first insulating later and the second insulating layer; etching the silicon layer to expose the first insulating layer, a central portio

Abstract: An apparatus for the rapid thermal processing of a semiconductor wafer is disclosed. The apparatus includes a preheat unit for preheating a gas composition, and a RTP reactor having a processing chamber and a heat source for heating the wafer. The processing chamber has a wafer holder, and a gas inlet and a gas outlet through which the preheated gas composition flows in and out of the processing chamber.

Abstract: A method for distinguishing a specific region in a sample to be observed by a microscope is disclosed. The method includes the steps of (a) forming a first concavity on a first side of the specific region by a focus ion beam (FIB) technique, (b) forming a second concavity on a second side of the specific region opposite to the first side by the focus ion beam technique, and (c) filling the first concavity and the second concavity with a first metallic packing and a second metallic packing respectively for defining the specific region to be observed.

Abstract: A plate-tilting apparatus adapted to be used in a semiconductor-manufacturing process is disclosed. The plate-tilting apparatus is used for preventing thin wafers from being collected in a cassette contacted with each other after the thin wafers are taken out of a solution. It includes a plate having the container locked thereon and having a first edge pivotally connected to a basal plane of a tank used in the semiconductor-manufacturing process, and a plate-lifting device connected to a second edge of the plate opposite to the first edge for lifting the second edge of the plate, so that the plate can be tilted at a specific angle.

Abstract: A wafer load/unload apparatus used to load/unload the wafer into/from the clamp ring for performing the E-Gun evaporation process is disclosed. The apparatus comprises a base, a central cylinder and a plurality of peripheral cylinders. The base has an even upper surface, and the central cylinder and the plurality of the peripheral cylinders are connected to the upper surface of the base respectively, wherein the plurality of the peripheral cylinders are located around the central cylinders. A recessed trench penetrating through sidewalls of the central cylinder is formed on a top surface of the central cylinder. The central cylinder can penetrate through a clamp ring, wherein the clamp ring is used to load a wafer for performing the E-Gun evaporating process. The spacing distances between the plurality of peripheral cylinders and the central cylinder are bigger than the width of the clamp ring.

Abstract: The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.

Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.

Abstract: An apparatus is provided for treating a wafer under fabrication with an erosive plasma, in a contamination controlled environment. The apparatus includes a chamber for containing the wafer to be treated by the plasma, and for isolating the wafer from contaminants external to the chamber during treatment. The chamber also includes one or more plasma erosion resistive screws. Each screw has a shaft secured within the chamber so that the shaft is unexposed to the plasma, and a raised head which is integral with, and made of the same material as, the shaft. The head has a continuous, surface shape with a reduced number of edges so as to reduce the accumulation of charge thereon, thereby resisting erosion by the plasma.

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a).

Abstract: A process of manufacturing a trench capacitor having a hill structure includes the steps of providing a semiconductor substrate, forming a passivation layer on the semiconductor substrate, etching the passivation layer to form a trench defined by a side wall and a bottom surface, forming a spacer on the side-wall, wherein the bottom surface includes a first part covered by the spacer and a second part exposed from the spacer, forming a sacrificial layer between the spacer and the second part, and removing the sacrificial layer until the spacer has been fully removed to expose the first part wherein an etched rate of the sacrificial layer is slower than that of the spacer, thereby forming the trench capacitor with the hill structure.

Abstract: A method of in situ reactive gas plasma treatment is disclosed. The method is capable of removing a residue remained in a metal etching chamber after the metal etching process to improve the yield of the wafer and the particle performance of the metal etching chamber. The method includes the steps of (a) vactuating the metal etching chamber after the metal etching process, (b) introducing a reactive gas to the metal etching chamber, and (c) applying an electromagnetic power to the metal etching chamber for producing a plasma derived from the reactive gas to remove the residue inside the metal etching chamber and/or on the wafer.

Abstract: An apparatus and related method for preventing leakage of process gases or liquids from a semiconductor wafer processing system, such as an oxidizing furnace. A specific embodiment of the present invention provides a method of preventing leakage of process gases or liquids from a joint of external piping and piping in a semiconductor wafer processing system. The method includes installing as the external piping a tube. The tube has a flange shaped to accommodate an O-ring. The method also includes providing an O-ring for use with the flange, and fastening the O-ring between the flange and the piping with a fastening mechanism to prevent leakage of process gases or liquids from the joint. Yet another embodiment provides a retrofit to existing external piping. A further embodiment provides an apparatus for processing semiconductor substrates that includes use of the O-ring, fastening mechanism and tube with flange.

Abstract: In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

Abstract: The present invention discloses a method to detect organic contamination in process environment of integrated circuits by using hemispherical-grain polysilicon layer that is formed in the process environment. The organic residue will contaminates the substrate which the hemispherical-grain polysilicon layer is formed thereon so as that the grain size of the polysilicon layer is between about 0.2 to 0.4 micrometers. The grain size of the hemispherical-grain polysilicon layer that is fabricated in a clean process environment is between about 0.5 to 0.8 micrometers. In other words, if organic contamination is residual in process environment, the grain size of the hemispherical-grain polysilicon layer that is fabricated in the process environment is smaller than a certain size to determine that the process environment is contaminated by organic contamination.

Abstract: This present discloses a method for making a concave bottom oxide within a trench, the steps comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; defining the insulating layer to form an opening exposing the surface of the semiconductor substrate; dry-etching the exposed semiconductor substrate within the opening by using the first insulating layer as an etching mask to form a trench; depositing a first oxide layer conformably over the insulating layer, the side-walls and the bottom of the trench; depositing a second oxide layer on the first oxide layer and filling-up the trench surrounded by the first oxide layer; annealing to densify the first and second oxide layers; etching-back the first and second oxide layer to remove the portion overlying the first insulating layer, and forming a spacer consisting of the residual first oxide layer on the side-walls of the trench, and a concave bottom oxide consisting of the first and second oxide layers on the bo

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract: The present invention provides a method for evenly immersing a wafer in a solution held in a solution chamber, which comprises the following steps: (1) placing at least one disk-shaped wafer inside a wafer holder which is used for vertically holding at least one wafer, (2) immersing the wafer holder into the solution vertically so that each wafer in the wafer holder can be vertically immersed into and react with the solution, (3) vertically rotating the wafer holder in the solution so as to invert each wafer in the wafer holder upside down, and (4) removing the wafer holder from the solution vertically after immersing the wafer in the solution for a predetermined period of time.