Abstract: The present invention relates to an auxiliary tool for assembling a scrubber which includes a motor, a shaft rotatably coupled to and extending through the motor, a shaft pin detachably connected to the shaft, and a disk coupled to the shaft and having a notch located relative to the shaft pin at a predetermined angle with respect to a longitudinal axis of the shaft when properly assembled. In specific embodiments, the auxiliary tool comprises a tool body configured to at least partially receive the motor, the shaft pin, the disk, and the notch of the disk. The tool body includes a first recess configured to at least partially receive the shaft pin and a protrusion configured to be at least partially received into the notch of the disk. The first recess and the protrusion are arranged at the predetermined angle to position the notch of the disk and the shaft pin of the scrubber for proper assembly at the predetermined angle with respect to the longitudinal axis of the shaft.

Abstract: Method and device for providing double cell density in synchronous dynamic random access memory (SDRAM) and in double data rate synchronous dynamic random access memory (DDR SDRAM) are disclosed. In specific embodiments, a conventional photolithography technology is used to define a cell area on a semiconductor substrate and then a trench capacitor is formed in the cell area. After that, an array device active area is defined on the cell area and STIs are formed beside the array device active area in the semiconductor substrate. Next, a polysilicon layer is subsequently deposited, photolithographed and anisotropically etched to form an array device polysilicon layer. A gate oxide layer, a gate conductive layer and a gate cap are subsequently formed on the semiconductor substrate and cell area according to the following steps in specific embodiments.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: According to the present invention, an apparatus for determining various processes of wafer fabrication suitable for a plurality of various processes of wafer fabrication, having: a plurality of wafer cassettes, each having a distinct transparency, used in the various processes of wafer fabrication; a sensor-set, used to detect the distinct transparency of each of the wafer cassettes, and output a signal corresponding to the distinct transparency; and an amplifier, connected to the sensor-set to receive the signal, thus reading the distinct transparency, so as to determine the type of the wafer cassettes. Furthermore, a method for determining various processes of wafer fabrication includes the steps of: providing a plurality of wafer cassettes, each having a distinct transparency, used in the various processes of wafer fabrication; reading the distinct transparency of each of the wafer cassettes; and determining the type of the wafer cassettes according to the distinct transparency.

Abstract: The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. An aspect of the present invention is directed to a method for determining a chemical mechanical polishing time for removing a target polishing thickness H from an uneven surface of a target wafer. The method comprises polishing a control wafer by a chemical mechanical polishing to obtain a progressive relationship of polishing thickness and respective polishing time therefor. A first polishing time T1 is determined for removing a first thickness H1 from the target wafer, in which the first thickness H1 with substantially the uneven surface removed is smaller than the target polishing thickness H of the target wafer to be removed.

Abstract: A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.

Abstract: A wafer supporting plate suitable for supporting a wafer during a semiconductor-forming process. In particular, the present invention relates to a wafer supporting plate capable of sensing the positioning condition of the wafer on the supporting plate during a heat treatment or other semiconductor-forming processes for detecting whether the wafer is being positioned normally on the supporting plate. The wafer supporting plate comprises a supporting plate body, at least three supporting props disposed on the supporting plate body for receiving and supporting a wafer, at least three sensing devices each disposed besides the supporting props and within the range encircled by the supporting props on the supporting plate body respectively.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data +½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A process of fabricating a deep trench capacitor includes the steps of: depositing a nitride masking layer over a substrate; removing portions of the nitride masking layer and substrate to form an exposed deep trench having sidewalls and a bottom surface; forming an oxide fill plug to fill a bottom portion of the trench; removing the oxide fill plug from the trench; doping a region of the substrate enveloping the bottom portion of the trench; depositing a spacer insulating layer over the sidewalls and bottom surface of the trench; removing a portion of the spacer insulating layer to expose a central portion of the bottom surface of the trench; depositing a conducting layer over the spacer insulating layer, and the exposed central portion of the bottom surface, the conducting layer and the doped region of the substrate being in electrical contact and forming a first plate of the capacitor; removing a portion of the conducting layer; removing the spacer insulating layer to expose outer walls of the conducting l

Abstract: Systems, methods, and computer program products for analyzing experiment results obtained in a process are provided. The process is conducted separately in a first and second state of a control variable to generate a first and second plurality of experiment data, respectively. The experiment data corresponds to a plurality of attributes of the process. A processor is included in the systems for comparing the first and second plurality of experiment data, and identifying attributes having a statistically significant difference in their corresponding experiment data obtained in the first and second state of the process. The identified attributes are then compared with attributes expected to be affected by changes in the control variable, which are contained in a know-how database, in order to create a conformity database and a non-conformity database.

Abstract: An LCD panel signal processor is disclosed. The LCD panel signal processor of the present invention is applied to an LCD panel having a gate driver and a source driver, and comprises: an input interface for receiving plural types of video signals; a micro-processing device for outputting a first control signal which controls the input interface to select a first type video signal from the plural types of video signals, converting the first type video signal into a digital video signal having an output format, and simultaneously sending an information signal to inform a panel controller of the output format. The panel controller receives the digital video signal according to the output format and generates a gate driver signal and a source driver signal for the gate driver and the source driver.

Abstract: A predecoder circuit for use in association with a memory circuit is shown to have a dynamic NAND gate formed by series-coupled transistors controlled by a bank active select signal and a row address selection signal. The predecoder circuit also includes a precharge circuit coupled to the dynamic NAND gate and controlled by a precharge signal. The predecoder circuit further includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and an output terminal selectively electrically connectable to at least one row decoder circuit for the memory circuit. The predecoder circuit finally includes a second inverter arranged in feedback with the first inverter to form a latch.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: An arbitration method and circuit for control of double data rate (“DDR”) dynamic random access memory (“DRAM”) device first-in, first-out (“FIFO”) registers which allows the data path of the device to be functional over a wider range of system clock and delay locked loop (“DLL”) clock signal skews. By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, it then attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast, that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: A system and method for finding operation/tool's combination which causes the integration failure in a semiconductor fabrication facility is disclosed. It comprises the steps of generating a candidate operation/tool list by selecting the operation/tool's that are more likely to cause said failure. Assign a weight value to each lot in the lot list for each operatioon/tool in said candidate operation/tool list, the weight value being a predetermined positive value for a bad lot, and a negative value for a good lot. Then select any pair of operation/tool's from said candidate operation/tool list and calculate a peak combination cumulative value for that pair of operation/tool's. Rank each pair of operation/tool's according to their corresponding peak combination cumulative values. It is determined the pair of operation/tool's with the greatest peak combination cumulative value the most likely to cause said failure.

Abstract: Embodiments of the present invention relate to an apparatus for spin drying substrates in a spin dryer tank. A spin dryer cover is movable between a closed position to close an opening of the spin dryer tank and an open position to open the spin dryer tank, and a cylinder is coupled with the spin dryer cover. The cylinder is movable in a first operation to move the spin dryer cover to the open position and movable in a second operation to move the spin dryer cover to the closed position. A system for sensing the position of the spin dryer cover comprises a cylinder sensor configured to sense the first operation and the second operation of the cylinder. A cover sensor is configured to sense the position of the spin dryer cover. A logic circuit is configured to output a cover opening signal indicating that the spin dryer cover is in the open position when the cylinder sensor senses the first operation of the cylinder and the cover sensor senses that the spin dryer cover is in the open position.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: A chemical mechanical polishing apparatus has a plurality of electric machines for executing mechanical polishing motions, at least two control systems for controlling the mechanical polishing motions, at least two signal wires connected with the two control systems for transmitting signals of the two control systems, and a wave filter comprising two terminals connected with the two signal wires respectively for filtering out the signal whose voltage exceeds a predetermined value in the two signal wires.