Patents Assigned to MoSys, Inc.
  • Method for generating a clock phase signal for controlling operation of a DRAM array
    Patent number: 6259651
    Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: July 10, 2001
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Clock phase generator for controlling operation of a DRAM array
    Patent number: 6147535
    Abstract: A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 14, 2000
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Method and structure for controlling operation of a DRAM array
    Patent number: 6078547
    Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: June 20, 2000
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung