Abstract: A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal.
Abstract: A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.
Abstract: A circuit applied to a television is provided. The television includes a memory and a display panel. The circuit includes an image processing circuit, a control circuit, an image capturing circuit and an output circuit. The image processing circuit processes image data to generate processed image data. The control circuit generates a control signal according to a switch signal. According to the control signal, the image capturing circuit captures the processed image data as predetermined image data and stores the predetermined image data to the memory. The output circuit transmits the predetermined image data to the display panel according to the control signal.
Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.
Abstract: A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.
Abstract: An embedded device, a RAM disk of an embedded device and a method of accessing a RAM disk of an embedded device are provided. The embedded device includes: a processing unit, configured to execute an operating system; a first memory, for the processing unit to access required system data when the processing unit executes the operating system; a function module, configured to perform a predetermined function; a second memory, for the function module to access required functional data through direct memory access when the function module performs the predetermined function; and a RAM disk driving module, configured to incorporate a first part of the first memory with the second memory to one RAM disk, and to control access of the RAM disk.
Abstract: A software update method applied to a television includes: downloading an update image file through a network, wherein the update image file includes an update script and a plurality of sets of data; storing the update image file to a memory; reading the update script from the memory; obtaining information of the data from the update script; sequentially reading the data from the memory according to the information; performing a padding operation on the data to generate a plurality of sets of padded data; and updating software in the television according to the padded data.
Abstract: A method for compressing image data is provided. The image data includes a file to be compressed, which includes N blocks to be compressed. The method includes: setting a target data increment of each of the N blocks of the file according to a 0th accumulated target data size and an Nth accumulated target data size; before compressing an nth block, calculating an (n?1)th accumulated target data size of an (n?1)th block according to the 0th accumulated target data size and the target data increment; when a difference between an (n?1)th accumulated compressed data size and the (n?1)th accumulated target data size is smaller than a predetermined threshold, removing X least significant bit(s) of a plurality of sets of data in the nth block to generate an updated nth block; and compressing the updated nth block to generate a compressed nth block.
Abstract: A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.
Abstract: A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.
Abstract: A video encoding apparatus for encoding a plurality of image blocks in a video frame includes an intra-frame prediction module, a transformation module and a quantization module. The intra-frame prediction module performs intra-frame prediction on the image blocks to generate a plurality of residual blocks. The transformation module performs a transformation on a target residual block along a predetermined direction according to a transformation matrix to generate a transformation result. The transformation matrix is a product of an initial transformation matrix and a secondary transformation matrix. The initial transformation matrix corresponds to a one-dimensional initial transform performed along the predetermined direction in a two-dimensional initial transform. The secondary transformation matrix corresponds to a one-dimensional secondary transform performed along the predetermined direction in a two-dimensional secondary transform. The quantization module quantizes the transformation result.
Abstract: A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.
Abstract: A multimedia communication apparatus, suitable for a first multimedia apparatus, is adapted to transmit or receive multimedia data and is electrically connectable to a standard connector. The standard connector may be non-reversibly or reversibly connected to a plug of a standard cable, and includes a plurality of the pins. The pins include multiple differential signal pins serving as multiple multimedia channels, a power pin serving as a power line, a first polarity pin, a first data pin and a ground pin. The multimedia communication apparatus includes a control logic and a multimedia signal processor. The multimedia signal processor transmits or receives multimedia data to/from a second multimedia apparatus through the multimedia channels, and further power handshakes or exchanges information with the second multimedia apparatus. The information is for controlling a multiplexer to switch the multimedia channels.
Abstract: A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.
Abstract: A receiver includes a bias current source, a comparator and an output circuit. The bias current source is powered by a first voltage source, and generates a bias current according to a second voltage source. The first voltage source is higher than the second voltage source. The comparator, coupled to the bias current source, compares two input signals to generate a comparison signal according to the bias current. The output circuit is powered by the second voltage source, and generates an output signal according to the comparison signal. The output signal and the second voltage source belong to the same power domain.
June 1, 2017
Date of Patent:
January 22, 2019
MSTAR SEMICONDUCTOR, INC.
Chun-Chia Chen, Jian-Feng Shiu, Chia-Chi Liu
Abstract: An electrostatic discharge (ESD) protection apparatus is provided. A first power rail provides first reference voltage. A second power rail provides a second reference voltage. A detection circuit generates a detection result according to whether ESD stress occurs on the first power rail. A first N-type MOSFET has its gate serving as a control terminal. A second N-type MOSFET has its gate serving as a second control node. An intermediate power rail provides an intermediate voltage between the first and the second reference voltages. A first switching circuit couples the first control node to the intermediate power rail or to the first power rail according to the detection result. A second switching circuit couples the second control node to the second power rail or to the first control node according to the detection result.
February 8, 2018
Date of Patent:
January 8, 2019
MSTAR SEMICONDUCTOR, INC.
Federico Agustin Altolaguirre, Yen-Hung Yeh, Po-Ya Lai
Abstract: A method for detecting a notch band is applied to a multicarrier communication system that operates in a wideband. The method includes: receiving a received signal, and generating a plurality of frequency-domain signals according to the received signal; performing a magnitude operation on the frequency-domain signals to obtain a plurality of magnitude values; determining a plurality of ratios of a first magnitude set among the magnitude values to a second magnitude set among the magnitude value to determine whether the received signal contains a notch band.
Abstract: An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals.
Abstract: An input interface circuit is provided. When a pad voltage is higher than a default operating voltage, a clamping circuit maintains the voltage at a first node at the default operating voltage. A first inverter is coupled between the first node and a second node. A voltage of a third node is adjusted along with the pad voltage (input end of a high-voltage buffering circuit) and the voltage at the second node, and causes the voltage at the third node has a same voltage change trend as the pad voltage. A second inverter is coupled between the third node and a fourth node. A voltage recovery circuit has its input end coupled to the fourth node and its output end coupled to the third node, and selectively couples the third node to a power line or a ground line according to the voltage at the fourth node.
Abstract: A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.