Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.

Abstract: A device applied to a display includes a receiving circuit, a detecting circuit, an image processing circuit and a response time enhancing circuit. The receiving circuit receives an input image signal. The detecting circuit detects a frame rate of image data of a frame in the input image signal. The image processing circuit performs image processing on the image data of the frame to generate a target pixel value of multiple pixels in the frame. The response time enhancing circuit determines multiple adjusted pixel values of the multiple pixels according to the frame rate, and outputs the adjusted pixel values to a display panel. For a pixel, the adjusted pixel values generated for the pixel under different frame rates are different.

Abstract: A circuit applied to a display apparatus includes a front-end circuit, a conversion circuit and an impulsive interference detection circuit. The front-end circuit converts an analog input signal into a digital input signal. The conversion circuit, coupled to the front-end circuit, converts the digital input signal from a time domain to a frequency domain to generate a frequency-domain signal. The impulsive interference detection circuit, coupled to the conversion circuit, detects a noise intensity of the frequency-domain signal to generate a detection result, which is used to determine whether the analog input signal has impulsive interference.

Abstract: A circuit applied to a playback device includes an image format determining circuit, a control circuit, an image processing module and a blending circuit. The image format determining circuit receives an image signal and determines whether the format of the image signal is a standard dynamic range (SDR) or a high dynamic range (HDR) to generate a determination result. The control circuit generates a control signal according to the determination result. The image processing module selects an image processing setting corresponding to one of the SDR format and the HDR format, and processes the image signal according to the image processing setting to generate a processed image signal. The blending circuit superimposes an interface image onto the processed image signal to generate an output image signal to a display.

Abstract: An apparatus for eliminating impulse interference includes an impulse interference detecting unit, an impulse interference eliminating unit and a control unit. The impulse interference detecting unit detects whether impulse interference exists in an input signal according to a predetermined condition, and generates an impulse interference eliminating request when having detected that the input signal satisfies the predetermined condition. In response to the impulse interference eliminating request, the impulse interference eliminating unit performs an impulse interference eliminating process on the input signal to generate an output signal. According to an output signal quality index associated with the output signal, the control unit selectively adjusts the predetermined condition used for detecting whether the impulse interference exists.

Abstract: A communication device includes: a computing circuit, performing a Jth power operation according to a first plurality of time-domain signals to generate a first plurality of computed signals; a transforming circuit, coupled to the computing circuit, transforming the first plurality of computed signals to a first plurality of frequency-domain signals according to a time-frequency transformation; a control circuit, coupled to the converting circuit, performing an absolute value operation on the first plurality of frequency-domain signals to generate a first plurality of output signals; a selecting circuit, coupled to the control circuit, selecting a maximum output signal satisfying a check condition from the first plurality of output signals; and a frequency estimating circuit, coupled to the selecting circuit, estimating a carrier frequency offset according to the maximum output signal.

Abstract: A signal receiving apparatus includes a signal processing circuit, an adjacent-channel interference (ACI) filter and an ACI detecting circuit. The signal processing circuit performs a signal processing process on an input signal to generate a processed signal. The ACI filter filters out ACI from the processed signal to generate a filtered signal. The ACI detecting circuit detects an energy difference between the processed signal and the filtered signal, and provides the energy difference to the signal processing circuit as a reference for adjusting the signal processing process.

Abstract: A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series.

Abstract: A method for controlling an image capturing device includes: calculating luminance data of a first image to generate a plurality of first characteristic values, and calculating luminance data of a second image to generate a plurality of second characteristic values; calculating a plurality of motion values of a plurality of blocks of the second image according to the luminance data of the first image and the luminance data of the second image; determining a plurality of ratio parameters corresponding to the blocks of the second image according to the motion values; generating a plurality of adjusted second characteristic values according to the ratio parameters, the second characteristic values and the first characteristic values; and generating an adjustment signal for controlling the image capturing device according to the adjusted second characteristic values.

Abstract: A decoding apparatus includes an input power estimating circuit, an error correction decoder and a controller. The input power estimating circuit generates multiple estimated input powers for multiple sets of data included in a packet that needs to be corrected, and calculates respective power differences between the multiple estimated input powers and a reference power. The controller determines one or multiple candidate error positions according to one of the multiple power differences that is higher than a predetermined threshold. The error correction decoder performs a decoding process on the packet according to the one or multiple candidate error positions.

Abstract: A signal receiving end of a digital television includes: an analog-to-digital converter (ADC), converting an input signal from an analog format to a digital format, the input signal including a target signal and an interference signal; a digital gain control circuit, coupled to the ADC, adjusting an amplitude of the target signal according to a gain; a detecting module, coupled to the digital gain control circuit, detecting a variance in the gain to generate a detection value; and a control circuit, coupled to the digital gain control circuit, determining a gain setting parameter according to the detection value. Wherein, the digital gain control circuit further updates the gain according to the gain setting parameter.

Abstract: An echo detection circuit for a multi-carrier system includes a memory, a threshold generating circuit and an echo determining circuit. The memory stores a plurality of channel impulse response values of the multi-channel system. The channel impulse response values include a target channel impulse response value, a plurality of preceding channel impulse response values and a plurality of subsequent channel impulse response values; a threshold generating circuit, coupled to the memory, generating a threshold corresponding to the target channel impulse response according to the preceding channel impulse response values and the subsequent channel impulse response values; and an echo determining circuit, coupled to the threshold generating circuit and the memory, comparing the target channel impulse response value with the threshold to determine whether the target channel impulse response value corresponds to an echo path of the multi-carrier system.

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

Abstract: A control circuit applied to a display includes an adjustment parameter generating circuit, an adjustment circuit, a compensation circuit, an image detail compensating circuit and an output circuit. The adjustment parameter generating circuit determines an adjustment parameter according to a backlight intensity corresponding to a pixel in a frame. The adjustment circuit adjusts a pixel value of the pixel according to the adjustment parameter to generate an adjusted pixel value. The compensation circuit compensates the adjusted pixel value according to a compensation curve go generate a compensated pixel value. The compensation curve includes a non-linear segment. The image detail compensating circuit generates a detail compensation value according to an edge factor of the pixel. The output circuit adjusts the compensated pixel value according to the detail compensation value to generate an output pixel value of the pixel.

Abstract: A method for writing images into a memory is provided. The method includes steps of: establishing a first configuration table for configuring the memory into a plurality of first buffers according to a first resolution of a first image; establishing a second configuration table for configuring the memory into a plurality of second buffers according to a second resolution of a second image, wherein the second resolution is different from the first resolution; and determining a position to which the second image is to be written into the memory according to the first configuration table and the second configuration table.

Abstract: A symbol decision method includes: storing a look-up table (LUT) to a symbol decision circuit; receiving a first signal, and generating a coordinate signal set corresponding to the first signal according to the first signal, wherein the coordinate signal set is located in a first decision region; and reading the LUT according to the coordinate signal set to output a first symbol corresponding to the first signal, wherein the first symbol is a first constellation point corresponding to the first decision region.

Abstract: A method for video decoding includes: dividing a plurality of luma component data of a reference frame into a plurality of primary data and a plurality of secondary data, respectively stored in a first memory region and a second memory region; accessing the first memory region to perform a motion estimation; and accessing the second region to perform a luma motion compensation.

Abstract: A data processing method of a multimedia device is disclosed. The multimedia device pauses playback of multimedia data in response to a pause signal. The method includes: buffering the multimedia data before the pause signal is received to obtain prerecorded multimedia data; writing the prerecorded multimedia data into a storage unit in response to the pause signal; reading the prerecorded multimedia data from the storage unit in response to a playback signal; and playing the prerecorded multimedia data.

Abstract: A receiving circuit capable of estimating frequency offset includes a front circuit and a calculation circuit. The front circuit receives a remote signal to generate a received signal. The calculation circuit includes: an exponentiation module, calculating an exponent of a power to generate a high-order signal; a frequency-domain transform module, performing frequency-domain transform on the high-order signal to generate a spectrum; a peak searching module, searching for a peak of the amplitude of the spectrum to generate a peak coordinate value reflecting a frequency where the peak occurs; an offset estimating module, adding the peak coordinate value with a compensation value to generate a sum, dividing the sum by a first divisor to generate a remainder, subtracting the compensation value from the remainder to generate a difference, and dividing the difference by a second divisor to generate an offset estimation value reflecting the frequency offset.

Abstract: A time-domain equalizer includes a delay circuit, a weighting circuit, a controller and a summation circuit. The delay circuit receives an equalized signal and accordingly generates M delayed signals for an equalized signal. The weighting circuit applies an mth weighting of M weightings to an mth delayed signal of the M delayed signals to generate an mth weighted signal. The summation circuit sums up the M weighted signals, according to which the equalized signal is updated. The controller iteratively updates the M weightings according to a vector {right arrow over (e)}n,p=[en,p,1 . . . en,p,M], where the symbol en,p,j is defined as en,p,j=?k(z[k]*z[k?Dp,j]*), the symbol n is an iteration index, k is a sample index, z[k] is a kth sample of the equalized signal, j is an integer index between 1 and M, and Dp,j represents a time delay amount corresponding to a jth delayed signal of the M delayed signals.