Abstract: A touch control system includes first and second sensing regions. At least one sensor monitors the first sensing region to generate a first sensing amount. At least one second sensor monitors the second sensing region to generate a second sensing amount. An initial coordinate generating module generates an initial coordinate according to the first and second sensing amounts, and determines whether a touch point is in an intersection region. When the determination result of the initial coordinate generating module is affirmative, a correction value generating module generates a correction value according to the first and second sensing amounts. A corrected coordinate generating module multiplies the initial coordinate by a first weight to generate a first weighted result, multiplies the correction value by a second weight to generate a second weighted result, and adds the first and the second weighted results to generate a corrected coordinate.

Abstract: An image synchronization method for a three-dimensional (3D) display apparatus is provided. The method includes steps of: receiving a plurality of first-eye image frames and a plurality of second-eye image frames; selecting a first image frame from the first-eye image frames according to a system time; selecting a second image frame from the second-eye image frames according to a timestamp of the first image frame; and outputting the first image frame and the second image frame.

Abstract: A sensing method for a sensing electrode cluster is provided. The sensing electrode cluster includes a plurality of groups, each comprising a plurality of bars. The sensing method includes scanning each of the groups according to a first scanning sequence, and scanning each of the groups according to a second scanning sequence, and determining a sensing position according to the first position and the second position. The first scanning sequence is different from the second scanning sequence.

Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.

Abstract: An audio decoding method is provided. In the audio decoding method, a synchronization word and a corresponding packet header are inserted at the beginning of each packet data. A position of the packet data is confirmed according to the synchronization word, and the packet data is then decoded according to information in the packet header. Accordingly, when an error occurs during the decoding process, the decoding process skips to a next packet data for decoding to avoid noise. In addition, a packet header can be directly accessed in the situation of a fast-forward operation to obtain decoding information of the packet data to perform audio decoding.

Abstract: A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage.

Abstract: A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

Abstract: A sensing electrode structure formed on a substrate of a touch device is provided. The sensing electrode structure includes: a first sensing electrode row; a second sensing electrode row, parallel to the first sensing electrode row, including a plurality of second sensing electrode units; and a guard ring, surrounding the second sensing electrode row, including a plurality of guard electrodes arranged between each two of the second sensing electrode units.

Abstract: A sound collecting system includes a plurality of microphones, a distance estimation module and an adjustment module. The distance estimation module estimates a distance to a user to accordingly provide a user distance. The adjustment module adjusts a part or all of the positions of the microphones according to the user distance.

Abstract: An output circuit adapted for an integrated circuit is provided. The output circuit includes a driver, a pre-driver and a buffer circuit. The driver is electrically connected to two output nodes outside the integrated circuit to output signals. The pre-driver controls the driver, and includes a load and an input transistor connected in series. Between the load and the input transistor is a connection node for controlling the driver. The buffer circuit controls the load and the input transistor according to an internal signal. Before turning off the input transistor, the buffer circuit pre charges the connection node through the load.

Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Abstract: A method for designing a pattern of sensing channels is provided. The method is applied to a touch panel including a plurality of electrodes and a plurality of sections of sensing channels. The electrodes are connected to a plurality of sensors for the touch panel via the sections of sensing channels. According to a minimum sensing channel width, a minimum sensing channel gap, a maximum distribution width and lengths of the sections of sensing channels, a set of rules are established. According to the set of rules, a programming process is utilized to determine respective widths of the sections of sensing channels.

Abstract: A control chip for controlling a player with a multimedia playback function and a data processing function is provided. The control chip includes: a multimedia playback module, being adapted to drive the multimedia playback function, configured to generate multimedia playback information associated with multimedia data that has been played; a data processing module, being adapted to drive the data processing function, configured to generate data processing information associated with data that has been processed; and a data protection module, configured to control at least one of the multimedia playback module to stop the multimedia playback function and the data processing module to stop the multimedia playback function according to the multimedia playback information and the data processing information.

Abstract: A calibration system for a display device is provided. The calibration system includes an image signal source, a user-motion sensing module, a control module, and a calibration interface. The image source drives the display device to display a reference image and an indication icon included in the reference image. The user-motion sensing module detects a user motion and generating a corresponding sensing result. The control module controls the image signal source to move the indication icon according to the sensing result. After selecting a region to be calibrated in the reference image by the indication icon through the user-motion sensing module, a user can adjust an image characteristic parameter of the display device that corresponds to the region to be calibrated through the calibration interface.

Abstract: An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage.

Abstract: Techniques are provided aimed at improving the flexibility and reducing the area and power consumption of digital baseband integrated circuits by using stream data processor based modem architecture. Semiconductor companies offering baseband ICs for handsets, face the challenges of improving die size efficiency, power efficiency, performance, time to market, and coping with evolving standards. Software defined radio based implementations offer a fast time to market. Dedicated hardware designs give the best die size and power efficiency. To combine the advantages of dedicated hardware with the advantages of conventional software defined radio solutions the stream data processor is partitioned into a stream processor unit, which implements processing functions in dedicated hardware and is hence die size and power efficient, and a flexible stream control unit which may be software defined to minimize the time to market of the product.

Abstract: A signal processing system includes a variable gain amplifier, an analog-to-digital converter (ADC), a gain compensation module and a signal processing module. The variable gain amplifier applies a variable gain to an analog input signal to generate an amplified analog signal. The ADC converts the amplified analog signal to an amplified digital signal. The gain compensation module applies a compensation gain to the amplified digital signal to generate a compensated signal. The compensated signal has an instantaneous change lower than a predetermined threshold. The signal processing module performs a signal processing procedure on the compensated signal.

Abstract: A method for detecting a primary synchronization is provided. The method includes: obtaining a time-domain signal sequence for synchronization; obtaining a correlation result corresponding to the time-domain signal sequence; normalizing the correlation result according to a received signal strength indicator corresponding to the time-domain signals; and sorting the normalized correlation result to ascertain a peak value position corresponding to the correlation result.

Abstract: A method of processing secure services is provided. The method is applied to a processing unit of a computing device to control the processing unit to process multiple secure services. The computing device includes a storage unit. The method includes: controlling a core of the processing unit to perform following steps in a secure mode: accessing the storage unit to obtain a first command that includes first secure service information, processing a first secure service associated with the first secure service information according to the first command, and accessing the storage unit to obtain a second command that includes second secure service information. During a period from a time point that the core accesses the storage unit to obtain the first to a time point that the core accesses the second command, the core is controlled to stay in the secure mode.

Abstract: A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.