Abstract: The present disclosure is directed to accelerometer measurement compensation for a device with first and second accelerometers. The first and second accelerometers are included in first and second components, respectively, of the device that are configured to rotate with respect to a hinge. The device detects a stuck condition of the first accelerometer, and compensates acceleration measurements of the first accelerometer by exploiting redundant information from the second accelerometer and applying a runtime calibration of undesired offsets.

Abstract: A computer-implemented method includes generating, by a computing system, a message including a status and editable data regarding a transaction request. The status indicates a potential delay related to the editable data. The computer-implemented method further includes receiving, by the computing system, an indication regarding the editable data. The indication includes a change to the editable data that remedies the potential delay by correcting information required to complete the transaction request.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: An exhaust gas purification catalyst or the like may inhibit poisoning of a noble metal component by a Si-containing compound generated or detached from silicon carbide, may inhibit degradation of exhaust gas purification performances over a long period, and may have excellent long-term durability. An exhaust gas purification catalyst may have a stacked structure including at least a substrate and a first and second coat layer, in that order. The substrate may be selected from a silicon carbide carrier including silicon carbide and a silicon carbide-covering carrier on which a coating layer including silicon carbide is provided. The first coat layer may include a compound including one or more alkaline-earth metals selected from Mg, Ca, Sr, and Ba. The second coat layer may includes one or more platinum group elements selected from Rh, Pt, and Pd.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

Abstract: A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.

Abstract: An electronic device receives data including an application update module for an application program, the application update including a first part, the first part including first update information and an indication value. A processor of the electronic device then compares the first update information with reference information associated with the indication value and stored in a memory of the electronic device. The processor then installs a second part of the application update module when the first update information corresponds to the reference information, thereby producing an updated application program.

Abstract: Systems and techniques for social responsibility load balancer are described herein. First user data for a first user and second user data for a second user is obtained. The first user data is aggregated into a first dataset and the second user data is aggregated into a second dataset. The first dataset and the second dataset are evaluated using a responsibility prediction learning model to determine a set of responsibilities. A target responsibility delta is calculated. The set of responsibilities are processed using a responsibility balancing algorithm to sort the set of responsibilities into the first responsibility assignments and the second responsibility assignments. A current delta is calculated between the first responsibility assignments and the second responsibility assignments. It is determined that the current delta is equal to the target responsibility delta. A user interface is generated to output the first responsibility assignments and the second responsibility assignments.

Abstract: A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

Abstract: A test circuit is configured to test and calibrate an impedance of a driver of an integrated circuit. Testing the impedance includes driving first and second currents through the driver via a first contact pad and a ground metallization of the integrated circuit. Testing the impedance includes measuring the voltage at a test metalization while driving the first and second current while the test metalization is successively coupled to the first contact pad and the ground metallization while driving the first and second test currents.

Abstract: A computer system selects a default payment account based on at least one of (a) account balance information for a plurality of accounts of a user or (b) user preferences received from the user. The computer system receives a request for a transaction to transfer funds to a recipient and determines that the transaction causes the account balance of the default payment account to decrease below a user-defined threshold minimum value. The computer system generates a screen display including a link associated with a second account and provides the screen display to a mobile device of the user. The computer system receives a selection of the link associated with the second account, generates an optical code associated with the second account that incorporates a tokenized account number of the second account, and transmits the optical code to the mobile device for the transaction.

Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

Abstract: Systems and methods involve an automated risk assessment platform server that receives data regarding a potential fraudulent account event from a fraud detection platform processor and a data mining function that extracts additional data related to the potential fraudulent account event from a plurality of data sources. An artificial intelligence engine function enhances the additional data for further processing, and a pattern recognition function searches the data for one or more data patterns that indicate whether or not the account event is fraudulent and generates a treatment recommendation when at least one data pattern is found that indicates that the account event is fraudulent.

Abstract: A user computing device comprises a network interface, an input/output (“I/O”) device, an imaging device, and a processing circuit storing instructions that cause a processor to receive a set of user photographs, determine an emotive state of the user in each of the photographs in the set of user photographs, categorize each of the photographs based on the determined emotive states of the user where each of the photographs is categorized into at least one of a user positive emotion category and a user negative emotion category, receive spending behavior data indicative of a spending behavior of the user, generate an advertisement based on the received spending behavior data where the advertisement includes a photograph from the set of user photographs categorized within at least one of the user positive emotion category and the user negative emotion category, and present the advertisement to the user via the display device.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: A voltage regulator has a first output is connected to a capacitive element. A current source is coupled between the first output and a first node receiving a power supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a set point voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

Abstract: Described herein is a lock system (e.g., for a vehicle door) including an NFC circuit in communication with a microcontroller that monitors the voltage of a battery (e.g., the vehicle battery). The microcontroller switches the NFC circuit to card emulation (CE) mode with energy harvesting capability when the battery voltage falls below a threshold so that the NFC circuit can harvest energy from a nearby Qi wireless charging field and store that harvested energy in an energy storage device. When the energy storage device is sufficiently charged, it is used power the microcontroller and an electronically actuated mechanical lock (e.g., vehicle door lock), then the microcontroller cooperates with the NFC circuit to switch the NFC circuit to NFC reader mode and attempt to verify a nearby NFC device. If the NFC device is verified, the microcontroller operates the lock, otherwise, it maintains the lock in an inactive state.