Abstract: A semiconductor device includes a first chip structure that includes a memory structure and a cell routing interconnection structure that is electrically connected to the memory structure, a second chip structure that is on the first chip structure and includes a first peripheral circuit, a second peripheral circuit, a first peripheral routing interconnection structure that is electrically connected to the first peripheral circuit and the cell routing interconnection structure, and a second peripheral routing interconnection structure that is electrically connected to the second peripheral circuit, and a connection structure that extends into the first chip structure and the second chip structure, where the connection structure includes: a first connection pad, a second connection pad that overlaps the first connection pad, and an intermediate connection structure that is between the first connection pad and the second connection pad and is electrically connected to the second peripheral routing interconnecti

Abstract: A semiconductor package including a package substrate, a plurality of photonics bridge chips located on the package substrate, a molding layer located on the package substrate, surrounding the plurality of photonics bridge chips, and including a plurality of via electrodes, and a plurality of chiplets located on the molding layer and the plurality of photonics bridge chips, the chiplets each including a photonics chip and a semiconductor chip located on the photonics chip, wherein the plurality of chiplets are spaced apart from each other in a horizontal direction, and at least two chiplets adjacent to each other from among the plurality of chiplets overlap one photonics bridge chip from among the plurality of photonics bridge chips in a vertical direction.

Abstract: A semiconductor package includes a package substrate, a plurality of stacked structures on the package substrate, each stacked structure including a plurality of core chips stacked on each other, each core chip including a memory cell array including a plurality of memory cells, a buffer chip on the package substrate, and spaced apart from the plurality of stacked structures in a horizontal direction, and a photonics package including an optical integrated circuit chip on the package substrate, an electronic integrated circuit chip on the optical integrated circuit chip, and a first molding layer surrounding side surfaces of the electronic integrated circuit chip, wherein the buffer chip is configured to control the memory cell of the core chip of each of the plurality of stacked structures.

Abstract: A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.

Abstract: A system for generating electricity with reduced or negative carbon emissions includes a power plant section having an electricity generating unit that includes a solid oxide fuel cell (SOFC) system. The SOFC system includes a SOFC fuel cell reactor and a combustor with an energy exchange path. The combustor is coupled to the fuel cell reactor to combust unutilized fuel. The system also includes a direct air capture (DAC) section having a carbon dioxide (CO2) adsorption device having a CO2 adsorbent material and a ventilator electrically coupled to the electric generator for flowing ambient air through the CO2 adsorption device in a carbon capture mode. The CO2 adsorption device is coupled to and in energy communication with the energy exchange path for releasing adsorbed CO2 in a carbon release mode.

Abstract: An electrode assembly includes a first electrode assembly having first multiple windings of a first laminate, the first laminate including a first electrode, a separator, and a second electrode, a middle portion surrounding the first electrode assembly and a second electrode assembly that surrounds the middle portion, the second electrode assembly having second multiple windings of a second laminate, the second laminate including a first electrode, a separator and a second electrode, wherein the middle portion adjusts a gap between the first electrode assembly and the second electrode assembly according to pressure changes.

Abstract: The present invention relates to battery lock electronics (1) for a battery unit (4) having a battery management system (3), the battery lock electronics (1) having: a) a first electronic interface (1a) with a battery management system (3), b) a second electronic interface (1b) with a communication device (2) and c) a processor unit (1c) connected to the first (1a) and to the second interface (1b), and performing, upon detection of an unlock signal via the second interface (1b): reading out of a battery state-of-charge value (7) from the battery management system (3), storing an upper threshold value (8) in the battery management system (3), storing a lower threshold value (9) in the battery management system (3), and determining from the battery state-of-charge value (7): the upper threshold value (8) which is determined to be greater than the battery state-of-charge value (7) by a predetermined upper value; the lower threshold value (9) which is determined to be lower than the battery state-of-charge va

Abstract: A battery comprising a shell and a roll core disposed within the shell, the shell including a shell body and an end cap component, one end of the shell body being provided with an opening, another end of the shell body being provided with a sealing portion, the opening being plugged by the end cap component, the roll core including a first tab and a second tab, the end cap component being provided with a pressure-relief structure, an outside wall of the sealing portion being provided with a first terminal and a second terminal at intervals, the first terminal and the second terminal being insulatively disposed, the first tab being connected to the first terminal, and the second tab being connected to the second terminal.

Abstract: A battery case for a pouch-type secondary battery accommodates an electrode assembly therein, and includes a first case, a second case configured to cover the first case, a cup portion provided in at least one of the first case or the second case and has a space formed to accommodate the electrode assembly, and a side portion formed along an outer circumference of each of the first case and the second case. The side portion includes a sealing portion sealed by bringing the first case and the second case into contact with each other. The side portion also includes an insulation failure-preventing portion formed between the sealing portion and the cup portion and configured to accommodates a sealing material melted in the sealing portion. A battery case shaping apparatus and a secondary battery manufacturing method are also provided.

Abstract: The present disclosure relates to a battery pack configured to accommodate a battery module including a cell stack in which a plurality of cells are stacked, including: a pack case including a base plate configured to support a lower portion of the battery module, a main partition wall coupled to a center portion of the base plate and formed to extend across the base plate, a side wall coupled along an edge of the base plate, and an auxiliary partition wall having both ends coupled to the main partition wall and the side wall, respectively; and a long bolt member coupled to the pack case by passing through the auxiliary partition wall such that the auxiliary partition wall is coupled to the main partition wall and the side wall.

Abstract: A battery module of the present disclosure includes: a plurality of battery cells each including an openable venting portion on a first surface, a bus bar assembly electrically connecting the plurality of battery cells, a cover portion covering the plurality of battery cells and including a through-hole in an area corresponding to an openable venting portion of a battery cell of the plurality of battery cells, and a cap portion covering the through-hole and detachably coupled to the cover portion.

Abstract: A battery cell including a stack and a first internal terminal. The stack includes: C cathode electrodes each including a cathode current collector, a cathode active layer arranged on the cathode current collector, and an external connector extending from the cathode current collector; A anode electrodes each including an anode current collector, an anode active layer arranged on the anode current collector, and an external connector extending from the anode current collector; and S separators, where C, A, and S are integers greater than one. Each one of the external connectors, of one of the C cathode electrodes and the A anode electrodes, includes a first tab and a second tab extending farther than the first tab, the second tabs are folded onto the first tabs, and the first internal terminal is laser welded onto the second tabs.

Abstract: The present disclosure provides an antenna device including a ground plane, a plurality of omni-directional antennas connected to the ground plane, a directional antenna connected to the ground plane, and a wall structure including a metal and connected to the ground plane, the wall structure surrounding the directional antenna and disposed between the directional antenna and the plurality of omni-directional antennas

Abstract: A method of operating a modem chip in a wireless communication device configured to perform multiple-input and multiple-output (MIMO)-based communication with an external device, includes: receiving channel state information for a channel between the wireless communication device and the external device; generating a channel matrix corresponding to the channel based on the channel state information; generating an input matrix of a preset first size based on a size of a fixed input of a universal neural network model, and the channel matrix; generating an output matrix of a preset second size based on the input matrix and the universal neural network model; and determining a precoding matrix based on the output matrix. The size of the fixed input of the universal neural network model is based on a maximum value of at least one of parameters adjustable in the MIMO-based communication.

Abstract: An optical transceiver includes a reception unit, a transmission unit, and a power control circuit. The reception unit converts a reception signal from an optical signal into an electrical signal. The transmission unit converts a transmission signal from an electrical signal to an optical signal. The power control circuit switches whether to supply the power supplied from the power supply unit to the reception unit or the transmission unit on the basis of whether an optical signal is transmitted or received.

Abstract: Presented are systems and methods for determining downlink/uplink timing. A network node may determine a downlink timing of a first link or a second link based on at least one of a first downlink timing or a second downlink timing. The first downlink timing may correspond to a first frequency band for the first link. The second downlink timing may correspond to a second frequency band for the second link. The network node may determine an uplink timing of the first link or the second link based on at least one of a first uplink timing or a second uplink timing. The first uplink timing may correspond to the first frequency band. The second uplink timing may correspond to the second frequency band.

Abstract: Provided in the embodiments of the present disclosure are an information transmission method and apparatus, and a storage medium. The method comprises: sending SRS antenna switching capability information to a network device, wherein the SRS antenna switching capability information comprises first information, and the first information is used for indicating one or more pieces of the following information: a UE not supporting an SRS antenna switching mode in a first set, the UE not supporting SRS antenna switching, one SRS antenna switching mode in the first set that is supported by the UE, and a plurality of SRS antenna switching modes in the first set that are supported by the UE; receiving SRS configuration information, which is sent by the network device, wherein the SRS configuration information is determined by the network device on the basis of the SRS antenna switching capability information; and sending an SRS on the basis of the SRS configuration information.

Abstract: A wireless transmit/receive unit (WTRU) may monitor a common physical downlink control channel (PDCCH) search space for a downlink control information (DCI) signal and a first radio network terminal identifier (RNTI). In an example, the DCI signal may include an uplink (UL)/downlink (DL) configuration indication. In a further example, the first RNTI may be associated with UL/DL configuration information. The WTRU may transmit UL data or receive DL data based on the received UL/DL configuration indication. In another example, the DCI may include a plurality of UL/DL configuration indications. In an additional xample, a plurality of WTRUs may monitor the common PDCCH search space for the first RNTI. Also, the UL/DL configuration indication may indicate UL/DL configuration information on a symbol basis. Further, the WTRU may receive a second RNTI which is associated with the UL/DL configuration indication.

Abstract: A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium for retrieving information from a server. Methods can include a server receiving a set of client-encrypted queries. The server identifies a set of server-encrypted decryption keys and transmits the set to the client device. The server receives a set of client-server-encrypted decryption keys that includes the set of server-encrypted decryption keys encrypted by the client device. The server also receives a set of client-encrypted/client-derived decryption keys that were derived by the client device. The server generates matching a map that specifies matches between the set of client-server-encrypted decryption keys and the set of client-encrypted/client-derived decryption keys. The server filters the set of client-encrypted queries using the map to create a set of filtered client-encrypted queries and generates a set of query results.