Patents Assigned to Napatech A/S
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Patent number: 10848422Abstract: A system and a method for receiving data packets at the inputs of two data handlers. Each data handler compares address data in the individual data packet with a first and a second list of addresses and forward packets to each other, so that data packets with one of the first addresses are fed to one data handler and packets with one of the second addresses are fed to the other data handler. The data handlers output the data packets received so that one data handler outputs all packets with addresses of the first addresses and the other data handler outputs all packets with addresses of the second addresses.Type: GrantFiled: December 12, 2017Date of Patent: November 24, 2020Assignee: Napatech A/SInventors: Michael Milde Lilja, Claus Ek
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Patent number: 10693796Abstract: Embodiments provide a system and method for network tracking. By using packet capture applications having a flow identifier and a time stamper, one or more raw packets from one or more packet flows intercepted from a network can be tagged with a unique identifier and timestamp that can later be used to aggregate packet flows that have been analyzed by one or more capture applications. The unique identifier can relate to the network interface of the particular capture application and can also have an increasing value, where the increase in value can be monotonic. Later capture applications, while capable of generating secondary timestamps, can disregard those secondary timestamps for the primary timestamp of the first capture application in order to remove complications arising from latency issues.Type: GrantFiled: December 3, 2018Date of Patent: June 23, 2020Assignees: International Business Machines Corporation, Napatech A/SInventors: William A. Bird, Russell Couturier, Vijay Dheap, Patrick V. Johnstone, Ben A. Wuest, Alex Omø Agerholm
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Patent number: 10601729Abstract: Embodiments are directed to a packet capture ring that provides a single network tap for packet capture and a series of processors (or appliances) for handling serialization and search request processing in a confederated and highly scalable manner. One such appliance (a “primary” appliance) maintains a tap port to the network. Each packet capture appliance has a locally attached repository that stores raw packets and a juxtaposed index that allows for retrieval of those packets. The primary appliance sends a single copy of encapsulated packets in opposite directions around the ring to its descendants. A designation is made across the system as to a “currently designated” appliance for servicing requests for indexing and storage of captured packets. This current designation shifts from appliance to appliance in the system, as a “previously designated” appliance has its storage capacity filled.Type: GrantFiled: June 26, 2018Date of Patent: March 24, 2020Assignees: International Business Machines Corporation, Napatech A/SInventors: William A. Bird, Russell Couturier, Thomas D. Silliman, Wayne Tackabury, Alex Omo Agerholm, Michael Milde Lilja, Peter Dahl Ekner, Philip Due Soeberg
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Patent number: 10467196Abstract: The invention relates to a method for storing files in a data storage. The method comprises steps of providing the data storage with a plurality of data files all having the same predetermined size and a step of subsequently storing new data in the data storage by including the new data in a new data file having the predetermined size and overwriting an existing data file with the new data file.Type: GrantFiled: September 30, 2016Date of Patent: November 5, 2019Assignee: Napatech A/SInventors: Hans-Martin Brændmose Jensen, Michael Milde Lilja
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Patent number: 10211939Abstract: Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.Type: GrantFiled: June 27, 2014Date of Patent: February 19, 2019Assignee: Napatech A/SInventor: Nicolai Asbjørn Smitt
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Patent number: 10033665Abstract: A system and a method for analyzing a plurality of data packets where the data packets are analyzed to determine which of a number of subsequent process(es) is/are to further analyze the data packets. Information identifying the subsequent process(es) is added to a FIFO. An unknown data packet type is not immediately recognizable, whereby a storage location is reserved in the FIFO, and the data packet is fed to a separate characterizing process deriving the information relating to the relevant process(es), which information is subsequently fed to the relevant storage location in the FIFO, so that the order of data packets represented in the FIFO is the order of receipt of the data packets. From the FIFO, information is fed to a work list or storage of the relevant subsequent processes to process the pertaining data packets. This processing may also be in the chronological order of receipt of the data packets.Type: GrantFiled: November 11, 2014Date of Patent: July 24, 2018Assignee: Napatech A/SInventor: Jens Christophersen
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Patent number: 9811110Abstract: A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.Type: GrantFiled: October 28, 2015Date of Patent: November 7, 2017Assignee: Napatech A/SInventors: René Krog Josiassen, Søren Kragh
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Patent number: 9800336Abstract: A network card or the like with two or more connectors having reflecting sides, where a light emitter is positioned between or behind the connectors and emit light toward the reflecting sides which act as a wave guide and guide the light to an opening between the connectors and toward the surroundings.Type: GrantFiled: January 8, 2015Date of Patent: October 24, 2017Assignee: Napatech A/SInventor: Sune Graves Krohn
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Patent number: 9729259Abstract: A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the parallel data path from knowledge of the clock controlling the parallel data path as well as which of the parallel lanes the part is output on.Type: GrantFiled: August 30, 2012Date of Patent: August 8, 2017Assignee: Napatech A/SInventor: Peter Ekner
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Publication number: 20160277322Abstract: A system and a method for analysing a plurality of data packets where the data packets are analysed to determine which of a number of subsequent process(es) is/are to further analyse the data packets. Information identifying the subsequent process(es) is added to a FIFO. An unknown data packet type is not immediately recognizable, whereby a storage location is reserved in the FIFO, and the data packet is fed to a separate characterizing process deriving the information relating to the relevant process(es), which information is subsequently fed to the relevant storage location in the FIFO, so that the order of data packets represented in the FIFO is the order of receipt of the data packets. From the FIFO, information is fed to a work list or storage of the relevant subsequent processes to process the pertaining data packets. This processing may also be in the chronological order of receipt of the data packets.Type: ApplicationFiled: November 11, 2014Publication date: September 22, 2016Applicant: Napatech A/SInventor: Jens Christophersen
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Patent number: 9407581Abstract: An apparatus and a method where a plurality of physically separate data receiving/analyzing elements receive data packets and time stamp these. A controlling unit determines a storing address for each data packet based on at least the time stamp, where the controlling unit does not perform the determination of the address until a predetermined time delay has elapsed after the time of receipt.Type: GrantFiled: December 6, 2010Date of Patent: August 2, 2016Assignee: Napatech A/SInventors: Peter Korger, Peter Ekner
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Patent number: 9246850Abstract: A method and apparatus adapted to prevent Head-Of-Line blocking by forwarding dummy packets to queues which have not received data for a predetermined period of time. This prevention of HOL may be on an input where data is forwarded to each of a number of FIFOs or an output where data is de-queued from FIFOs. The dummy packets may be provided with a time stamp derived from a recently queued or de-queued packet.Type: GrantFiled: December 27, 2011Date of Patent: January 26, 2016Assignee: Napatech A/SInventor: Søren Kragh
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Patent number: 9155224Abstract: A printed circuit board having an electronic component which is to be cooled by a cooling surface biased thereon, where the biasing elements are abutted not by the PCB but a stiffer element attached to the PCB in order to not strain or bend the PCB.Type: GrantFiled: April 19, 2011Date of Patent: October 6, 2015Assignee: NaPatech A/SInventors: Claus Ek, Christoffer Storemoen
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Patent number: 9155223Abstract: A thermally controlled assembly having two parallel PCBs defining there between, and by the aid of a channel forming element, a channel in which air is forced, using a fan, to cool components in the channel. The fan has a cooling surface cooled by air from the fan and which is biased toward an element provided in a space below the cooling surface. The forced air also drawing air from outside the assembly through the space and into the channel to cool other elements provided in the space.Type: GrantFiled: April 19, 2011Date of Patent: October 6, 2015Assignee: NaPatech A/SInventor: Claus Ek
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Patent number: 8934341Abstract: An assembly and a method where a number of receiving units receive and store data in a number of queues de-queued by a plurality of processors/processes. If a selected queue for one processor has a fill level exceeding a limit, the packet is forwarded to a queue of another processor which is instructed to not de-queue that queue until the queue with the exceeded fill level has been emptied. Thus, load balancing between processes/processors may be obtained while maintaining an ordering between packets.Type: GrantFiled: December 6, 2010Date of Patent: January 13, 2015Assignee: Napatech A/SInventor: Peter Korger
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Patent number: 8929378Abstract: An apparatus and method for analyzing a data packet, where the first and second information is derived relating to the data packet. The first information relates to a type of the data packet, a standard to which the data packet conforms and/or which data item(s) is/are present in the data packet. The first information is used for identifying a function into which the second information is input to generate third, and this third information is output together with at least part of the data packet.Type: GrantFiled: September 15, 2010Date of Patent: January 6, 2015Assignee: Napatech A/SInventor: Jens Christophersen
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Patent number: 8898339Abstract: In conventional systems the CPU is altered after a data frame has been received and the packet stored in a host buffer. This interrupts normal operation of the CPU and applications, which is determined to systems performance. The invention relates to a method of transferring data from a network to a host using a network analyzer card, where a plurality of data frames from a network link is received and a descriptor is added to the frame. The descriptor includes data about the frame; each data frame and its or their attached descriptor is transferred to a host memory.Type: GrantFiled: September 12, 2004Date of Patent: November 25, 2014Assignee: Napatech A/SInventors: William Mark Dries, Christopher Bloxham, Kathryn Elizabeth Rickard
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Patent number: 8874809Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.Type: GrantFiled: December 6, 2010Date of Patent: October 28, 2014Assignee: Napatech A/SInventor: Peter Korger
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Publication number: 20140211816Abstract: A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the parallel data path from knowledge of the clock controlling the parallel data path as well as which of the parallel lanes the part is output on.Type: ApplicationFiled: August 30, 2012Publication date: July 31, 2014Applicant: Napatech A/SInventor: Peter Ekner
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Publication number: 20130311609Abstract: An apparatus and a method for receiving and forwarding packets, where the packets are received by a number of adapters and fed to a common storage in addresses allocated by a controller. The controller is adapted to forward to the adapters requests and at the same time log which addresses have been allocated to each adapter. As a response to the request, the individual adapter forwards predetermined data to predetermined addresses in the storage so that the controller is able to update the available or the used addresses in the storage.Type: ApplicationFiled: January 11, 2012Publication date: November 21, 2013Applicant: NAPATECH A/SInventors: Søren Kragh, Peter Ekner