Patents Assigned to National Chip Implementation Center
  • Patent number: 8451078
    Abstract: A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: May 28, 2013
    Assignees: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: You-Liang Lai, Ying-Zong Juang, Hann-Huei Tsai, Sheng-Hsiang Tseng, Chin-Fong Chiu
  • Patent number: 8199510
    Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: June 12, 2012
    Assignees: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chin-Long Wey, Chi-Shi Chen, Chi-Sheng Lin
  • Patent number: 8172622
    Abstract: A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: May 8, 2012
    Assignees: National Chip Implementation Center, National Applied Research Laboratories
    Inventors: Chun-Ming Huang, Hui-Ming Lin, Chih-Chyau Yang, Chien-Ming Wu, Shih-Lun Chen