Abstract: A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

Abstract: A method of fabricating a single chip for integrating a field-effect transistor into a microelectromechanical systems (MEMS) structure is provided. The method includes the steps of: providing a substrate having thereon at least one transistor structure, a MEMS structure and a blocking structure, wherein the blocking structure encircles the MEMS structure to separate the MEMS structure from the transistor structure; forming a masking layer for covering the transistor structure, the MEMS structure and the blocking structure; forming a patterned photoresist layer on the masking layer; performing a first etching process by using the patterned photoresist layer to remove the masking layer on the MEMS structure; and performing a second etching process by removing a portion of the MEMS structure to form a plurality of microstructures such that a relative motion among the microstructures takes place in a direction perpendicular to the substrate.

Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Abstract: A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: A biochip package structure is provided. The biochip package structure includes a substrate, a biochip, at least one wire, and a molding compound. The substrate has a circuit unit electrically connected, by wiring, to the biochip defined with a sensing region. The molding compound covers the wire but leaves the sensing region of the biochip exposed, allowing a cavity to be formed in the sensing region. The cavity delivers a biomedical sample. The biomedical sample reacts in the sensing region. Thus, the biochip package structure is applicable to various medical and biochemical assays.

Abstract: A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased.

Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

Abstract: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures.

Abstract: In a symmetric crossover structure of two lines formed of a lower conductor layer and a higher conductor layer above a substrate, each of the two lines is branched to two routes at where they are crossed over to each other. The first route of the first line uses the higher layer to cross the first route of the second line and the lower layer to cross over the second route of the second line. The second route of the first line uses the lower layer to cross over the first route of the second line and the higher layer to cross over the second route of the second line. The two lines therefore have symmetric coupling effects to the substrate.