Abstract: A system and method for enabling a graphical program to natively access an external memory buffer are disclosed. The graphical program may execute within a graphical program execution environment, and the external memory buffer may be allocated by another program that executes externally from the graphical program and the graphical program execution environment. The graphical program may be executed concurrently with a producer program that stores data in the memory buffer, and/or with a consumer program that reads and uses the data from the memory buffer. The memory buffer may be located within a region of memory allocated by the producer program, by the consumer program, or by another program that executes externally from the graphical program and the graphical program execution environment, such as a memory manager program.

Abstract: Performing power quality and synchrophasor analysis on a resampled signal. A first signal may be initially received which corresponds to a power system. The first signal may have a plurality of cycles and may have a frequency that varies over time. One or more parameters may be determined from the first signal. Based on the one or more parameters, the first signal may be resampled to produce an even angle signal. Various power quality measurements may be performed on the even angle signal. Similarly, further processing may be performed to perform synchrophasor measurements, e.g., to determine phasor, frequency, and/or rate of frequency change for the first signal. In some embodiments, the resampling processing elements (e.g., circuitry, programmable hardware elements, processors and memories, etc.) may be shared between the two analysis.

Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.

Abstract: Measurements, e.g. S-parameter measurements may be performed by obtaining a complex ratio of at least two signals, using a single signal-receiver while eliminating noise problems traditionally associated with single receiver systems. A Vector Signal Generator (VSG) may be used to generate the input stimulus (signal), making it possible to share the local oscillator (LO) signal of the VSG with a single vector receiver, such that the phase noise of the LO signal is common to both the VSG and the vector receiver. When the stimulus signal from the VSG is observed with the vector receiver, the LO phase noise is unobservable, resulting in a significant reduction of the phase noise in the measured signals in both the numerator and the denominator, which in turn leads to a significant reduction in the phase noise of the ratio while retaining the benefits of a simple, single receiver.

Abstract: System and method for developing a circuit for QR decomposition with auxiliary functionality. A first function is included in a first program. The first function is configurable to specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt process. A second program is automatically generated based on configuration of the QR decomposition and the first function. The second program includes program code implementing the QR decomposition and the auxiliary function for the first function in the first program. A hardware configuration program (HCP) may be automatically generated based on the first program, including the second program, where the HCP is deployable to hardware, e.g., a programmable hardware element, thereby implementing the modified QR decomposition circuit, including the QR decomposition of the matrix A and the auxiliary function.

Abstract: Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal.

Abstract: Capturing datasets of interest from a data acquisition data stream. An acquired dataset may be received from a measurement device. The acquired dataset may include measurement data from measurements of one or more physical phenomena acquired by the measurement device, and may be a current dataset in a sequence of datasets acquired by the measurement device. The acquired dataset is buffered, resulting in a buffered dataset. One or more thresholds specifying datasets of interest may be automatically determined based on the buffered dataset or one or more previously acquired datasets. The buffered dataset may be automatically analyzed with respect to the one or more thresholds, and a determination may be made as to whether the buffered dataset is a dataset of interest based on said automatically analyzing. In response to determining that the buffered dataset is a dataset of interest, the buffered dataset may be stored in a storage medium.

Abstract: A mechanism for determining an error vector magnitude EVMTD for a signal transmitted by a device under test (DUT). A receiver (typically an RF signal analyzer) produces a baseband signal in response to the signal transmission. An OFDM input signal (derived from the baseband signal) is accessed from memory. The OFDM input signal includes a sequence of time-domain OFDM input symbols. A reference signal is accessed from the memory. The reference signal includes a sequence of time-domain OFDM reference symbols. EVMTD is computed in the time domain based on a time-domain difference signal, i.e., a time-domain difference between the sequence of time-domain OFDM input symbols and the sequence of time-domain OFDM reference symbols. The error vector magnitude EVMTD is determined without transforming the sequence of time-domain OFDM input symbols to the frequency domain. The error vector magnitude EVMTD is related to a standard-defined composite EVM by a scalar multiple.

Abstract: Devices and methods for synchronizing devices over a switched fabric. A master device maintains a global time, determines a mapping between the global time and a counter of a switch over a memory-mapped fabric, and sends the mapping to a slave device. A slave device maintains a local time, determines a first mapping between the local time and a counter of a switch, receives a second mapping between the counter and a global time of the master device, and synchronizes its local time to the global time based on the first and second mappings. The master and slave device may map their times to the counter by sending respective request packets to the switch and receiving respective completion packets including respective counter values from the switch. The master and slave device may determine respective time values corresponding to the respective counter values based on in-switch delays of the packets.

Abstract: A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement DC gain compensation using a programmable variable resistance. A MOS transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations. An integrated CMOS-based variable resistor may be thereby used for an analog adjustable attenuator. Master and slave CMOS transistors may be operated in linear mode, and temperature effects on the linear transistors may be compensated for by using an integral loop controller (current controller) configured around the master MOS transistor. Circuits implemented with the compensated variable resistance have a wide range of adjustment with a control voltage, and may be used in the front-end (circuits) of an oscilloscope or digitizer, or in any other circuit and/or instrumentation benefitting from an adjustable attenuator.

Abstract: System and method for rendering data with specified constraints. A request for data from a data set may be received. The data set may include time-stamped historical data, including multiple reduced data sets, each having a respective resolution. The request may specify a time frame. A first reduced data set of the reduced data sets may be determined based on the specified time frame. First data from the first reduced data set corresponding to the specified time frame may be retrieved, and are usable for display on a display device. The data set may be generated from received raw data, where the raw data includes time-stamped historical data at a first resolution. The raw data may be reduced via multiple stages, thereby generating the reduced data sets at their respective resolutions. The reduced data are generated and represented in a way that is visually pleasing and technically accurate.

Abstract: A switch system having a plurality of switch inputs, a plurality of switch outputs, a switch matrix comprising a plurality of N×N switching elements to selectively couple one or more of the plurality of switch inputs to one or more of the plurality of switch outputs during use to provide one or more paths for routing signals from one or more of the switch inputs to one or more of the switch outputs during use.

Abstract: A single semiconductor-based junction may be used to create a voltage reference, and temperature compensate the voltage reference, by time-multiplexing the voltage reference between different current drive levels. That is, the value of the current driven through the single junction may be repeatedly varied in a recurring manner. In case the junction is a zener diode, the current may be repeatedly switched between forward and reverse directions. As long as the temperature coefficients (in ppm/° C.) of the different voltages developed responsive to the different currents across the junction are different, a weighting of the different voltage values yield a zero temperature coefficient voltage reference value. To implement a bandgap reference, a single diode-connected bipolar junction transistor may alternately be forward-biased using a first current and at least a second current.

Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.

Abstract: Performing sequencing of a polynucleotide. A first image of microparticles that are distributed in a random fashion on a substrate may be received. Each of the microparticles may include a plurality of similar oligonucleotides of the polynucleotide. A second image of the microparticles may be received. A plurality of first subportions of the first image may be determined. Each subportion may include a respective plurality of microparticles distributed in a random fashion. The second image may be analyzed to identify a plurality of second subportions in the second image. Each of the plurality of second subportions may correspond to a respective one of the plurality of first subportions. A plurality of the microparticles may be matched from the first and second images based on said analyzing. At least a portion of the sequence of nucleotides of the polynucleotide may be determined based on said matching.

Abstract: Systems and methods for interoperating between a time-sensitive (TS) network and a non-time-sensitive (NTS) network. The system may include a TS network switch and a TS network interface controller (NIC). Each may have a functional unit. A first port of the TS switch may be coupled to an NTS node of the NTS network and its functional unit may be configured to manage insertion and removal of tags associating packets received from the NTS network with the NTS network. The tagged packets may be forwarded on to the TS NIC via a second port. The functional unit of the TS NIC may be configured to queue tagged packets received from the TS network switch and queue and tag packets destined for the NTS network via the TS network switch.

Abstract: Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.

Abstract: When compiling high-level, graphical code (e.g. LabVIEW™ code) to a different representation (e.g. different software code or hardware FPGA), information relating to characteristics of the design may be collected/captured from the compilation process, and automatically provided to all the earlier stages of the compilation process to obtain more optimal results. Without automated feedback of this information, users have to manually identify, produce, and provide the feedback information, or forego the process altogether, having to assume that the tool has produced the best possible results when that may not be the case. To correct timing, failed constraints paths may be parsed and compared to delays obtained during a previous compile, and previous adjustments that didn't yield desired results may be undone. The longest delay that didn't result from an undone path may then be identified, and adjusted, and the process may be repeated until all paths are predicted to pass.

Abstract: A touch-gesture wiring method for connecting data flow wires to input/output terminals of nodes in a graphical program is described. The method may be implemented by a graphical programming application that executes on a mobile device that includes a touch-sensitive screen configured to receive user input as touch gestures. The method may aid the user by displaying a magnified view of the input/output terminals that makes it easier (relative to the default view of the graphical program) for the user to see the input/output terminals and/or easier to select a desired one of the input/output terminals.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.