Abstract: An improved receiver system may include an input to receive an input signal, and a signal generating circuit to generate a desired oscillator signal that is a single sideband radio frequency signal of time varying frequency. The receiver may also include a downconversion stage to generate an intermediate frequency (IF) signal based on the input signal and the desired oscillator signal. A signal processing block in the receiver may be used to produce an output signal based on the IF signal by frequency shifting the IF signal by an amount that compensates for the time varying frequency of the desired oscillator signal. The desired oscillator signal may be generated using a vector signal generator that receives a control value from the signal processing block, converts the control value to a pair of analog input signals, and generates the desired oscillator signal by quadrature modulating the pair of analog input signals.

Abstract: System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

Abstract: Systems/methods for computing a power spectral density estimate for a noise signal. Where the noise signal appears in two channels (a single channel), n successive data acquisitions from the two channels (the single channel) are used to compute n respective cross (power) spectral densities, which are then averaged. The averaged cross (power) spectral density may then be smoothed in the spectral domain. The magnitude of the smoothed cross (power) spectral density comprises an estimate for the noise power spectral density. An effective number of independent averages may be computed based on the number n, the time-domain window applied to the acquired sample sets, the amount of overlap between successive sample sets, and the shape of the frequency-domain smoothing function. A statistical error bound (or uncertainty measure) may be determined for the power spectral density estimate based on the effective number of averages and the averaged single-channel and cross-channel spectral estimates.

Abstract: System and method for communicatively coupling a serial communication plug to a serial communication bus. The system may include a housing. The housing may include a receptacle that is configured to communicatively couple to a bus. The receptacle may include one or more internal retention springs situated inside the receptacle. The one or more internal retention springs may be configured to grip a male plug with a retention force, when the male plug is inserted into the receptacle. The housing may include or may be coupled to a clamp where the clamp is external to the receptacle. When the male plug is inserted into the receptacle, the clamp may be adjustable via a clamp adjustment mechanism to constrain the one or more internal retention springs, thus augmenting the retention force and further securing the male plug in the receptacle.

Abstract: System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion.

Abstract: An input protection circuit may include an input node to receive an input signal, and may further include an output node to provide a protected output signal based on the input signal. Protection circuitry may be coupled between the input node and the output node to establish a current path that bypasses the input node and pulls the output pin to a specified reference voltage level in the event of a transient at the input node. A push-pull power supply may be used to provide the reference voltage to the current path, and dissipate any excess voltage by burning it off in a semiconductor device included in the push-pull power supply circuitry.

Abstract: Techniques are disclosed relating to generating pilot sequences for channel estimation and/or equalization. In some embodiments, a generated pilot sequence has a flat frequency response, a null portion, and low autocorrelation. In some embodiments, a method for generating the pilot sequence includes: starting with a Constant Amplitude Zero Autocorrelation (CAZAC) sequence and iteratively performing, until the result has a flat magnitude: padding the sequence with zeros, determining whether a frequency transform (FT) of the zero-padded sequence has a flat magnitude, adjusting a phase of a second sequence (that has a desired frequency response) to match a phase of the FT, determining an inverse FT of the adjusted second sequence and using a result of the inverse FT as the sequence for the next iteration. The disclosed techniques may allow efficient production of pilot sequences for use in cellular networks, for example.

Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: Operating a programmable controller with a plurality of processors. The programmable controller may utilize a first subset of the plurality of processors for a scanning architecture. The first subset of the plurality of processors may be further subdivided for execution of periodic programs or asynchronous programs. The programmable controller may utilize a second subset of the plurality of processors for a data acquisition architecture. Execution of the different architectures may occur independently and may not introduce significant jitter (e.g., for the scanning architecture) or data loss/response time lag (e.g., for the data acquisition architecture). However, the programmable controller may operate according to any combination of the divisions and/or architectures described herein.

Abstract: System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information.

Abstract: Method and system for a test process. The method may include performing tests on one or more units under test (UUTs). At least one test on one or more UUTs may be performed. A signal may be acquired from the UUT. A reference signal may be retrieved. The reference signal may be derived from a transmitted signal characteristic of the UUT. The signal may be analyzed with respect to the reference signal. Results, useable to characterize the one or more UUTs, from performing the at least one test on the one or more UUTs may be stored. The reference signal may be derived from an initial test and may be stored for subsequent retrieval. A respective reference signal may be retrieved for all UUTs of the one or more UUTs for a respective test. The signal may be a radio frequency signal. The UUT may be a wireless mobile device.

Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt.

Abstract: Various embodiments are described of devices and associated methods for processing a signal using a plurality of vector signal analyzers (VSAs). An input signal may be split and provided to a plurality of VSAs, each of which may process a respective frequency band of the signal, where the respective frequency bands have regions of overlap. Each VSA may adjust the gain and phase of its respective signal such that continuity of phase and magnitude is preserved through the regions of overlap. The correction of gain and phase may be accomplished by a complex multiply with a complex calibration constant. A complex calibration constant may be determined for each VSA by comparing the gain and phase of one or more calibration tones generated with each region of overlap, as measured by each of the VSAs.

Abstract: Configuring wires/icons in a diagram. The diagram may be an executable diagram such as a graphical program or a system diagram. The diagram may include a plurality of icons that are connected by wires, and the icons may visually represent functionality of the diagram. The diagram may be executable to perform the functionality. Displaying the diagram may include displaying a first wire in the diagram, where the first wire connects a first icon and a second icon. Data transfer functionality may be specified for the first wire and/or the first or second icon in the diagram. The data transfer functionality may be visually indicated in the diagram, e.g., by appearances of the first icon, the second icon, the first wire, and/or icons displayed proximate to these components of the diagram.

Abstract: A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Abstract: Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.

Abstract: Systems and methods for interoperating between networks. A first network may be configured to operate according to a first real time network protocol and each of one or more second networks may be configured to operate according to respective second real time traffic protocols. A mapping may specify data routing between a plurality of ports and the routing may maintain real time behavior between the first network and the one or more second networks. Additionally, routing information may be inserted in packets routed from the one or more second networks to the first network and removed from packets routed from the first network to the one or more second networks. The packets may be routed, based on the mapping, to distinct queues for the first network and the one or more second networks for processing by an application executing on at least one device.

Abstract: System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread.

Abstract: A hybrid amplifier includes a linear amplifier coupled in series with a switching amplifier. The linear amplifier may generate an intermediate amplified signal according to an input signal. The switching amplifier may generate an output signal according to the intermediate amplified signal, the output signal having an amplitude with respect to a reference voltage provided at a reference node. The linear amplifier may drive the reference node to adjust the reference voltage responsive to transient changes in the output signal. A high-pass filter coupled to the linear amplifier and the switching amplifier may enable the switching amplifier to provide most of the steady-state current, which may drive a load, from actual ground. The linear amplifier and switching amplifier may be independently powered, for example from a power supply having a primary winding and two electrically isolated secondary windings that respectively provide power to the linear amplifier and the switching amplifier.