Abstract: A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.

Abstract: A test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit (e.g., a digital television video circuit). The test data is functionally to verify the subject circuit. The functional verification of the subject circuit is performed utilizing an output of the subject circuit generated responsive to the test data in accordance with an operational functionality of the subject circuit. The test data generator is also coupled to provide the test data to a built-in self-test (BIST) circuit so as to enable the built-in self-test circuit to receive the test data.

Abstract: Circuits, devices, and methods for enabling the digitization of scanned images with an Analog Front End (AFE) circuit. The AFE circuit includes a sampler for sampling a signal produced by an image sensor and in response generating analog image samples. The AFE circuit also includes a Programmable Gain Amplifier for generating amplified samples by amplifying the analog image samples. The AFE circuit further includes an Analog to Digital Converter for generating digitized samples from the amplified samples; and a Digital Programmable Gain Amplifier for amplifying the digitized samples which are subsequently presented to a processor for further processing of the scanned image. Accordingly, the scanned image is digitized with amplification taking place both in the analog and in the digital domain, deriving benefits from each. The AFE circuit may be calibrated in two steps, once for each of the domains.

Abstract: Circuits, devices and methods provide a phase delay and use it to select when an analog color signal is converted to digital. The phase delay is adjustable, which permits choosing a moment in time when conversion results in improved processing. A PLL circuit receives the synchronizing signal of the color signals, and generates phased signals. A phase adjuster generates an adjustable delay signal by mixing in suitable proportions two of the phased signals that are 45 degrees apart. The delay signal is used by an analog to digital converter, to adjust when exactly it is to be sampled.

Abstract: An assembly and method suitable for use in packaging integrated circuits including a support substrate for supporting an integrated circuit die embedded in a molded encapsulating cap. The substrate includes a conductive die attach pad adapted to be molded into the encapsulating cap. The pad includes an interior facing support surface and a spaced-apart exterior facing exposed surface defined by a peripheral edge. The support surface is adapted to support the embedded die, while the exposed surface is to be exposed from the encapsulating cap. The attach pad further includes a locking ledge portion extending outward peripherally beyond at least a portion of the exposed surface peripheral edge. This ledge is adapted to be subtended in the encapsulating cap in a manner substantially preventing a pull-out of the attach pad in a direction away from the encapsulating cap.

Abstract: A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a coprocessor which executes frame programs. The frame programs include instructions which address memory. The memory includes page addresses and byte addresses. The instructions of the frame program address the page addresses and byte addresses. A particular page address is reserved as a null page address, wherein any instruction addressing the null page address causes the memory locations of the most recently accessed memory page to be accessed.

Abstract: The present invention sets forth a process of making, and a device comprising, a capacitor with a damascene tungsten lower electrode. The capacitor is manufactured by first depositing an insulating nitride layer on a field oxide layer, followed by deposition of a layer of oxide on the nitride layer. A gap is etched into both the nitride and oxide layers, wherein a lower electrode comprising a damascene tungsten stud is deposited following deposition of a Ti/TiN liner for the stud. An oxide layer is next formed over the stud having a conducting tungsten channel with another Ti/TiN liner disposed therethrough and connecting with the stud. Then, a metal layer is deposited and etched to form both a contact for the stud via connection to the channel, and an upper electrode insulated from the contact.

Abstract: A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.

Abstract: An up/dn read prioritization protocol is used to select between multiple hits in a set associative cache. Each set has associated with it an up/dn priority bit that controls read prioritization for multiple hits in the set--the up/dn bit designates either (i) up prioritization in which the up direction is used to select the entry with the lowest way number, or (ii) dn prioritization in which the down direction is used to select the entry with the highest way number. For each new entry allocated into the cache, the state of the up/dn priority bit is updated such that, for the next cache access resulting in multiple hits, the read prioritization protocol selects the new entry for output by the cache.

Abstract: A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.

Abstract: A processing system removes the burden of maintaining legacy hardware by employing a system management mode mechanism to provide an environment for virtualizing preexisting memory and I/O space instructions into operations for high resolution raster graphics circuitry, thus maintaining functionality and backwards compatibility with preexisting software.

Abstract: A semiconductor bond pad prevents cratering by including an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

Abstract: A driver which is particularly suitable for use with a backplane transceiver logic bus in a computer system is disclosed. In a preferred embodiment, a MOSFET is connected such that its gate and source are in a feedback loop which includes an amplifier and a first switching MOSFET. The source and drain of the MOSFET are connected in a connection path from the bus to ground, and a second switching MOSFET is connected between the gate of the MOSFET and ground. The first and second switching MOSFETS are arranged such that they switch in opposition to each other (one being turned on when the other is turned off) and a CMOS input signal is connected to the gates of the switching MOSFETS. In one state of the driver the MOSFET is turned off, in the other state the feedback loop is closed and the MOSFET is conductive. The rise and fall times of the driver's output can be controlled independently of each other.

Abstract: A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery.

Abstract: A method of and apparatus for processing semiconductor wafers which include observing optical characteristics of exposed undeveloped photoresist, without removing the wafers from the stepper is disclosed. The present invention includes the steps of loading a wafer having a layer of photoresist into a photolithography system, exposing the photoresist in accordance with an initial set of control parameters including exposure time, position of the wafer within the photolithography system, and/or focus change. Prior to developing the photoresist, optical characteristics of the exposed photoresist are observed using a phase contrast microscope which detects latent images. Then, according to the observations of the latent image, the initial set of control parameters are adjusted to generate a second set of control parameters.

Abstract: A ferroelectric programming cell utilizable for providing programming signals for configurable logic elements. A preferred embodiment of the ferroelectric programming cell includes a volatile memory cell having first and second internal data storage nodes that are latched in complementary states when the volatile memory cells positive power input is held to a maximum allowed voltage level and its negative power input is held at ground. A node enabling switching means connected between an external signal generator and the volatile memory cell enables an external signal generator to set the values of the first and second complementary internal nodes. First and second substantially identical capacitance-dividers each include a first ferroelectric capacitance means for storing a non-volatile configuration state.

Abstract: A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register.

Abstract: A circuit for sampling a digital input signal utilizing an asynchronous strobe signal and a method for such synchronization are disclosed. The circuit includes an input storage element, such as a latch, which stores the input signal upon receipt of a strobe signal. There is a possibility that the input storage element will become temporarily metastable, with the output of the element being indeterminate, should the digital input signal change levels at substantially the time that the strobe signal is received. The subject synchronization circuit includes circuitry which senses when the input storage element is metastable and gating circuitry which produces a synchronized signal after receipt of the strobe signal, provided the input storage element is not metastable. The synchronized signal can then be used to clock the stored input signal.

Abstract: An improved tape automated bonding method of bonding the beam leads of lead frame tape to gold bumps formed on the contact pads of a semiconductor device, wherein the tape includes a plurality of interconnected beam leads defined by at least one opening in the tape such that each beam lead has an inner end and an outer end. The method includes the steps of depositing a gold layer on the beam leads, masking a region of each beam lead from further deposition of material such that a predetermined portion of each beam lead is exposed for further deposition of material, depositing a predetermined amount of tin on the exposed portion of each beam lead, establishing contact between each beam lead and the die bump to which each beam lead is to be bonded and applying a predetermined amount of pressure and heat to form a bond between each beam lead and the die bump to which the beam lead is to be bonded such that the bond formed includes the primary eutectic of the combination of tin and gold.

Abstract: A semiconductor memory device having a CMOS memory cell with a floating gate and increasing concentration of dopant in the source, drain and channel regions. Typically the concentration profile is generally exponential across the channel width. The device has relatively high diffusion current densities accelerated toward the surface and directed toward the channel/drain interface. Gate oxidation thickness is reduced over the channel near the drain to create a tunnel "window" in the area of greatest electric field magnitude. The device provides for significantly reduced write times as compared to conventional devices.