Patents Assigned to National Semiconductor
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Patent number: 11967351Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.Type: GrantFiled: April 12, 2022Date of Patent: April 23, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chia-Che Chung, Chia-Jung Tsen, Ya-Jui Tsou, Chee-Wee Liu
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Patent number: 11955384Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.Type: GrantFiled: February 17, 2022Date of Patent: April 9, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu
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Publication number: 20240112912Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: July 28, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
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Publication number: 20240111210Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: May 9, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
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Patent number: 11947828Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.Type: GrantFiled: August 20, 2021Date of Patent: April 2, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
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Publication number: 20240107903Abstract: A memory device includes a substrate, a 2-D material channel layer, a 2-D material charge storage layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The 2-D material channel layer is over the substrate. The 2-D material charge storage layer is over the 2-D material channel layer. The 2-D charge storage layer and the 2-D material channel layer include the same chalcogen atoms. The source/drain contacts are over the 2-D material channel layer. The gate dielectric layer covers the source/drain contacts and the 2-D material charge storage layer. The gate electrode is over the gate dielectric layer.Type: ApplicationFiled: March 13, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yen LIN, Po-Cheng TSAI
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Publication number: 20240105779Abstract: A method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.Type: ApplicationFiled: January 9, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yen LIN, Che-Jia CHANG
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Publication number: 20240102162Abstract: A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.Type: ApplicationFiled: February 1, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chun-Yi CHOU, Chih-Piao CHUU, Miin-Jang CHEN
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Patent number: 11942546Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.Type: GrantFiled: December 3, 2020Date of Patent: March 26, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITYInventors: Kuan-Ting Chen, Shu-Tong Chang, Min-Hung Lee
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Publication number: 20240096976Abstract: A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.Type: ApplicationFiled: January 6, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shih-Yen LIN, Po-Cheng TSAI
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Patent number: 11934916Abstract: An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.Type: GrantFiled: July 8, 2021Date of Patent: March 19, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jiun-Yun Li, Shih-Yuan Chen, Yao-Chun Chang, Ian Huang, Chiung-Yu Chen
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Publication number: 20240088228Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan WANG, Chih-Hsiang HSIAO, I-Chih NI, Chih-I WU
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Publication number: 20240088255Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Miin-Jang CHEN, Sheng-Han YI, Chen-Hsuan LU
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Publication number: 20240081077Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung UniversityInventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
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Publication number: 20240072054Abstract: A device comprises a first semiconductor layer, a dielectric layer, a second semiconductor layer, and a gate structure. The first semiconductor layer is over a substrate. The first semiconductor layer comprises a first channel region and first source/drain regions on opposite sides of the first channel region. The dielectric layer is over the first semiconductor layer. The second semiconductor layer is over the dielectric layer. The second semiconductor layer comprises a second channel region and second source/drain regions on opposite sides of the second channel region. The gate structure comprises a first portion extending in the dielectric layer, a second portion wrapping around the first channel region of the first semiconductor layer, and a third portion wrapping around the second channel region of the second semiconductor layer.Type: ApplicationFiled: April 24, 2023Publication date: February 29, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chien-Te TU, Chee-Wee LIU
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Patent number: 10311825Abstract: An LC display driver including a gamma reference circuit to generate N gamma-compensated reference voltages based on at least one pre-defined gamma curve divided into M regions defined by M+1 breakpoint voltages, each generated by a range-region DAC coupled to a subset of voltage taps of a range resistor string (some subsets overlapping). An output circuit generates the N gamma-compensated reference voltages, and includes a reference resistor string with N reference voltage taps, and M+1 breakpoint locations to receive respective breakpoint voltages, the N reference voltage taps divided into M subsets corresponding to the M regions of the gamma curve, each of the M subsets of reference voltage taps forming a voltage divider. N output selector circuits output a corresponding one of the N gamma-compensated reference voltages based on a respective reference voltage tap and the associated voltage divider.Type: GrantFiled: February 15, 2016Date of Patent: June 4, 2019Assignee: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Christopher Ludden, Imre Knausz
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Patent number: 10153383Abstract: An apparatus and method that controls the power produced by a string of solar cells, enabling the string to operate at its maximum power point when connected to a bus that operates at an externally controlled voltage. The apparatus and method can also be used to increase or decrease the output power of a string to any desired operating point.Type: GrantFiled: March 12, 2009Date of Patent: December 11, 2018Assignee: NATIONAL SEMICONDUCTOR CORPORATIONInventor: Andrew Foss
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Patent number: 10141749Abstract: One heuristic for tuning a wireless power transfer device includes monitoring a circuit parameter while sweeping a power source frequency; identifying two frequencies related to local maxima of the circuit parameter values; estimating self-resonant frequency of an electromagnetically coupled device based on the two frequencies; determining a value for a tuning component of the wireless power transfer device such that the device self-resonant frequency equals the estimated coupled device self-resonant frequency; and adjusting the tuning component to the determined value.Type: GrantFiled: November 30, 2015Date of Patent: November 27, 2018Assignee: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Vijay N. Choudhary, Robert Loke
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Patent number: 10042009Abstract: The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.Type: GrantFiled: October 27, 2015Date of Patent: August 7, 2018Assignee: National Semiconductor CorporationInventors: Philipp Lindorfer, Peter J Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa
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Patent number: 9863817Abstract: A battery temperature monitoring circuit, which has a cold comparator and a hot comparator, achieves high accuracy in a small cell size by utilizing a cold current optimized for the cold comparator and a cold reference voltage, and a hot current optimized for the hot comparator and a hot reference voltage, along with switching circuitry that provides the cold current to the cold comparator as the battery temperature approaches the cold trip temperature, and the hot current to the hot comparator as the battery temperature approaches the hot trip temperature.Type: GrantFiled: October 21, 2014Date of Patent: January 9, 2018Assignee: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Luan Minh Vu, Thomas Y. Tse, Tuong Hoang