Abstract: A method and apparatus for synchronizing a digital data demodulator to a received phase modulation carrier signal in which the carrier signal is phase shifted during each modulation period of the carrier to represent one of four pairs of binary bits or dibits. A dibit clock is adjusted to the phase of a reference dibit clock whose output is used to synchronize the demodulator in establishing the location of the modulation period of the incoming carrier. In order to overcome errors found in the decoding of the carrier signal, the adjustment of the dibit clock is suppressed when the dibits 00 and 10 are being decoded.

Abstract: A magnetic bubble domain memory device is provided that includes a magnetic domain data chip having a major-minor loop organization with on-chip firmware providing redundancy information enabling the use of the chip even though one or more defective minor loops may be present thereon. One of the pages is written in the minor loop, where a page is defined as a common bit position in each of the plurality of minor loops, with a series of magnetic domains having an odd total number. The next succeeding page in the minor loops contains a series of magnetic domains and voids which are representative of the loop numbers of defective minor loops on the chip with the remaining pages in the minor loops having an even number of magnetic domains contained in each of the pages. Collectively, the pages containing the odd and even number of magnetic domains together with the page containing the map of the defective minor loops comprise the on-chip firmware providing redundancy information.

Abstract: A switching regulated power supply operates over a broad range of input voltage and frequency, and outputs direct current power for computer equipment and the like. The power supply can be paralleled with identical power supplies, thereby satisfying any predetermined power requirement. A charge pump bulk voltage balancing circuit balances voltage on capacitors in an input rectifier and filter circuit. A flux sensing circuit senses magnetizing current in the secondary of a power transformer and the integrated signal is incorporated into pulse duration modulation to achieve dynamic flux balancing of the power transformer through a feedback loop. Output voltage of the power supply connects to a control supply of the power supply, providing power feedback to the control supply to maintain the operating parameters of the power supply as long as the output voltage does not fall below a predetermined level.

Abstract: Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.

Abstract: An integrated circuit for sequentially receiving a plurality of binary interval numbers, each representing the width of a time interval occurring during optical scanning of a bar coded label, includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes input logic circuitry for receiving and temporarily storing the binary interval numbers and a plurality of adders and shift registers for adding predetermined ones of the stored binary interval numbers and storing the resulting sums. The integrated circuit includes a plurality of comparators for comparing predetermined ones of the sums and stored sums to produce a plurality of intermediate signals. Encoding circuitry encodes predetermined ones of the intermediate logic signals to produce a digital character number representing a character scanned on the bar coded label and also includes output circuitry.

Abstract: A rotary ink jet printer has an ink supply in a rotating reservoir wherein a major portion of the ink supply is isolated from the ink feed system during the printing operation. A cylindrical reservoir has a central cavity and a surrounding or outer cavity connected by an orifice opened and closed by means of a ball valve to control the flow of ink or ink supply from the central cavity to the outer cavity.

Abstract: A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal.

Abstract: A method and apparatus for exposing a section of photographic medium such that it exhibits an incremental gradient in optical density across an area of the medium. A source of radiant energy is located in a container, which container is covered by a ground glass plate. This plate is covered by an opaque sheet, which sheet contains a narrow aperture. This sheet is covered by a second ground glass plate, such that the edge of the second plate overlies the edge of the aperture. A camera is focused on the surface of the opaque sheet. A portion of the light from the light source is diffused through the edge of the second plate and reflected toward the camera from the surface of the opaque sheet, causing the resultant image captured on the medium when the camera is activated to show a change in optical density with respect to the distance from the image on the medium of the edge of the second plate.

Abstract: An optical sensing member for reading a coded member having parallel aligned tracks of data and clocking coded symbols which includes a pair of sensing apertures offset to enable the sensing of the data track to occur out of phase with the sensing of the clocking track. The sensing member includes a housing having a sensing surface in which the offset apertures are located, a light source, a pair of photo-transistors for sensing the tracks of coded symbols and optical fibers for transmitting light from the light source to the tracks of coded symbols and the reflected light to the photo-transistors for the reading of the coded members.

Abstract: A system for loading a DC multiline plasma charge transfer device and for holding charges applied thereto. Each line of the device includes input and transfer electrodes positioned on opposing walls which define a channel confining an ionizable medium. The transfer electrodes comprise adjacent groups of four electrodes with two driven in common with like electrodes of all other lines, and with timing of pulses applied by the common drivers being regular and constant. A common driver is also utilized for the input electrodes of each line while logic control is applied to the input driver and to the other transfer electrodes for each line. With this system and with a minimum of drive electronics, the charges may be shifted to a desired location and in desired patterns along the length of the device. The charges may be held at the desired location by circulating the charges between a set of electrodes at the desired holding location including two commonly driven electrodes.

Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips generates data representing numerical characters encoded in the symbol. Scanning means generates signals in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip as valid and invalid characters, the valid characters being recognized by a second chip which stores the valid characters and enables a microprocessor chip to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip.

Abstract: A data processing system is disclosed in which a high-speed processor is added to a slow-speed processor and in which both processors have access to a first memory unit with the slow processor having access priority over the fast processor. In order to allow the fast processor to operate without losing data when a conflict occurs during a write operation, a second memory is coupled to the fast processor in which is stored all the data stored in the first memory. When the fast processor attempts to write into both memories but fails to write into the first memory due to a conflict with the slow processor, the data stored in the second memory is then transferred to the first memory subsequent to the completion of the access operation by the slow processor. This arrangement allows the fast processor to complete the write operation interrupted by the conflicts with the slow processor, thereby allowing the fast processor and the slow processor to have access to the same data.

Abstract: An apparatus which may be used, for example, for feeding a record medium in a printer. The apparatus includes a rotatable member having means thereon for connection to the platen of the printer, and also having teeth on the periphery thereof and a driving surface thereon. The apparatus also includes a rotatable driving unit having at least one driving member or camming lug thereon to engage the teeth and thereby incrementally rotate the rotatable member as the driving unit is rotated. The apparatus further includes a coupling means moveable between first and second positions whereby the coupling means is operatively disconnected from the driving unit and the rotatable member when the coupling means is in the first position, and whereby the coupling means when in the second position is effective to disconnect the camming lug from the teeth and to also operatively connect the driving unit with the driving surface to continuously rotate the rotatable member as the driving unit is rotated.

Abstract: A speed control circuit for a motor is responsive to variations in motor supply voltage and torque wherein a digital output indication of the actual speed of the motor is generated. The digital output is converted to an analog value and applied to a comparator which also receives the output voltage of a ramp circuit based on the motor supply voltage. The output of the comparator controls the width of the motor voltage pulses applied from a power amplifier to the motor in which the voltage pulses applied have proportionally larger width for a smaller level of motor supply voltages or decrease in the amount of motor shaft speed and proportionally narrow width pulses for increased levels of motor supply voltage or an increase in the amount of motor shaft speed. A one-shot network is provided for motor stall protection.

Abstract: A data store and retrieval system is disclosed in which a pair of RAM buffer memories are coupled to a CCD page main memory to provide high-speed read/write access by a computer to the main memory. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Compare means included in the system compares the page address requested by the computer with the page address stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for the requested data. Both read/write access is available under these conditions. If a no comparison is found, logic circuits located in the system using the requested page address transfer the page in which the requested address is located from the CCD main memory to the RAM buffer memories for access by the computer.

Abstract: An integrated circuit for sequentially receiving a plurality of digital character words produced in response to optical scanning of a bar coded label and a plurality of corresponding binary signals representing, respectively, validity, scanning direction, and timing of the digital character words includes first, second, third, and fourth sequentially located edges forming a rectangle. The integrated circuit includes input circuitry for receiving the digital character words and corresponding binary signals and further includes twelve shift registers for storing predetermined ones of the digital character words. Four frame counters and associated control circuitry responsive to the binary signals and the character words steer the incoming character words to predetermined ones of the shift registers. The integrated circuit outputs formatted character words to a digital processor system.

Abstract: A symbol processing system incorporated in an NMOS/LSI chip separates valid data from invalid data all generated by scanning a bar-coded symbol. The signals representing the bars and spaces of the symbol are decoded by a pattern recognition array, and the decoded data is clocked into a storage unit. When valid data is discovered, such data is captured within the storage unit. The valid data is then clocked out of the storage unit to a utilization device for further processing.

Abstract: A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.