Patents Assigned to NEC
  • Publication number: 20090208567
    Abstract: The present invention provides: a carbon nanohorn composite including a carbon nanohorn, a substance encapsulated in the carbon nanohorn, and a polyamine adsorbed by chemical reaction firmly to a surface functional group present on the opening part on the surface of the carbon nanohorn, wherein the release amount and release rate of the encapsulated substance can be controlled using the difference in size, substituent or three-dimensional structure of the polyamine, which is used as a plug; a method of controlling the release of the encapsulated substance; and a process for producing the carbon nanohorn composite. The release amount and release rate of the substance encapsulated in the carbon nanohorn composite is controlled by selecting a polyamine molecule, which plugs the opening part formed in the carbon nanohorn by oxidation, by its size, substituent or three-dimensional structure.
    Type: Application
    Filed: July 3, 2007
    Publication date: August 20, 2009
    Applicant: NEC
    Inventors: Ryota Yuge, Hideki Yorimitsu, Masako Yudasaka, Sumio Iijima
  • Publication number: 20090037506
    Abstract: A FFT circuit performs M×R×Q-point fast Fourier transform of received signals, wherein M is an over-sampling rate of the received signals, Q is a chip repetition unit and R is a chip repetition rate. A weighting multiplier multiplies a frequency component having frequency component number equal to an integral multiple of R among M×R×Q frequency components output from the fast Fourier transform circuit by a weighting coefficient for propagation channel equalization, and multiplies the frequency components other than the integral multiple of R. An inverse fast Fourier transform circuit receives outputs of weighting multiplier and performs inverse fast Fourier transform of the frequency component having a frequency number equal to the integral multiple of R.
    Type: Application
    Filed: February 7, 2006
    Publication date: February 5, 2009
    Applicant: NEC
    Inventor: Takashi Mochizuki
  • Publication number: 20020049605
    Abstract: The server device comprises a database for storing identification information for identifying the client in correspondence with an individual password assigned to the client, obtaining means for obtaining the telephone number information of the client transmitted via the communications line, and retrieving means for retrieving the identification information from the database based on the telephone number information obtained by the obtaining means. And when the telephone number information is authenticated as the information of the client according to the identification information retrieved by retrieving means, an image for returning the password is transmitted with respect to the client. And in the event the password returned from the client matches the password stored in the database, the services are provided from the server device to the client.
    Type: Application
    Filed: May 16, 2001
    Publication date: April 25, 2002
    Applicant: NEC
    Inventor: Kazuo Hagi
  • Patent number: 6268240
    Abstract: In a static memory cell including first and second drive MOS transistors, first and second MOS transfer transistors and first and second load elements, the drain of the first drive MOS transistor and the source of the first transfer MOS transistor are formed by a first impurity region in a semiconductor substrate, and the drain of the second drive MOS transistor and the source of the second transfer MOS transistor are formed by a second impurity region in the semiconductor substrate. Also, a first metal silicide layer is formed on the first impurity region and the gate of the second drive MOS transistor, and a second metal silicide layer is formed on the second impurity region and the gate of the the drive MOS transistor. Further, the first and second load elements are formed on the first and second metal silicide layers, respectively.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: July 31, 2001
    Assignee: NEC
    Inventor: Fumihiko Hayashi
  • Patent number: 5764092
    Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: June 9, 1998
    Assignee: NEC
    Inventors: Koji Wada, Minoru Akiyama
  • Patent number: 5734647
    Abstract: There is provided a CDMA communication system in which the number of multiple users can be greatly increased under fast fading circumstances. In a transmitting apparatus, an M-ary digital modulator modulates the m-bit (m.gtoreq.2 and m is an integer) binary digital signal into M-value symbols (M=2.sup.m) prior to the spreading operation by multipliers. In a receiving apparatus, after the despreading operation by an orthogonalizing filter, an M-ary digital demodulator compensates the variation of the phase and amplitude of the carrier of the M-ary modulated signal during the transmission. A decision circuit decides the output of the M-ary digital demodulator. A tap coefficient control circuit calculates orthogonalizing coefficients using the outputs of the subtractors, the outputs of the M-ary digital demodulator, the outputs of receiving filters, and the spreading code.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: March 31, 1998
    Assignee: NEC
    Inventors: Shousei Yoshida, Akihisa Ushirokawa
  • Patent number: 4855694
    Abstract: A lumped element circulator comprises a dielectric substrate having a conductive layer on an upper center portion of its upper surface and a lower conductive layer entirely on its lower surface. A conductive pedestal frame structure is soldered to the upper conductive layer of the dielectric substrate on the outer periphery of a ferromagnetic substrate secured to the upper conductive layer of the dielectric substrate. Capacitors are mounted in recesses formed on the pedestal frame structure. A plurality of overcrossing parallel conductive strip lines extend in pairs across the ferromagnetic substrate with 120 degrees angular separation at their centers. One end of each strip line pair is short-circuited by a terminating conductor located substantially on the same horizontal plane as the upper electrodes of the capacitors and connected thereto, allowing them to be interconnected by short connecting leads and further to input/output ports.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: August 8, 1989
    Assignee: NEC
    Inventor: Hiroshi Ogawa
  • Patent number: 4634643
    Abstract: Herein disclosed are a mask for X-ray exposure composed of a X-ray absorbing layer of tungsten having a desired pattern, a membrane transparent to X-ray and supporting the X-ray absorbing layer, a frame member reinforcing and supporting the membrane at the periphery thereof and films of titanium and/or nickel provided between the membrane and the X-ray absorbing layer. The mask makes it possible to obtain an accurate replication of extremely fine patterns and the desired pattern of the mask can be prepared by the direct dry etching of the X-ray absorbing layer using a resist pattern as the etching mask.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: January 6, 1987
    Assignee: NEC
    Inventor: Katsumi Suzuki
  • Patent number: 4633441
    Abstract: Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting state of the counter at an optional value, a selection circuit for consecutively selecting the array in response to the output of the counter, and a control circuit for advancing the state of the counter in response to a shift pulse.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: December 30, 1986
    Assignee: NEC
    Inventor: Shoji Ishimoto
  • Patent number: 4631425
    Abstract: A logic circuit on a semiconductor chip having a decoding or a selecting function has at least two input transistors coupled in parallel between an output node and a reference point. Input signals are applied to the input transistors, and an output is derived from the output node. Instead of employing inverters to produce complement signals, a conductivity of one input transistor is made different from that of the other input transistors. The proposed logic circuit can decode or select a combination pattern of input signals without using a complement signal producing circuit. Therefore, the number of circuit elements and signal lines are decreased.
    Type: Grant
    Filed: January 31, 1984
    Date of Patent: December 23, 1986
    Assignee: NEC
    Inventor: Shigeru Koshimaru
  • Patent number: 4628330
    Abstract: An ink-jet recording apparatus applies a pressure, which is higher than atmospheric pressure, to an ink supply. A recording head includes a nozzle for jetting ink droplets. A valve is disposed between the pressurized ink supply and the nozzle in order to control the ink flow to the nozzle. The valve is opened in response to a recording signal only when ink droplets are to be jetted from said nozzle.
    Type: Grant
    Filed: January 24, 1986
    Date of Patent: December 9, 1986
    Assignee: NEC
    Inventors: Michihisa Suga, Mitsuo Tsuzuki
  • Patent number: 4627051
    Abstract: In a loop network system comprising a plurality of stations connected by a loop-shaped transmission path (38) wherein each station may utilize the transmission path, the improvement wherein the stations are divided into a clock station and node stations between which control and priority functions are distributed. The clock (30) station transmits, to the path at a predetermined period, a synchronization signal block serving to trigger the node stations (31-36) and to define a highest degree of priority for transmission. A trigger signal block is also transmitted from the clock station to the path so as to define a lower degree of priority each time when a transmission right is seized by the clock station within the predetermined period. Each of the node stations transmits a transmission signal block to the path by seizing a transmission right in consideration of the degree of priority indicated by each of the synchronization and the trigger signal blocks.
    Type: Grant
    Filed: January 30, 1986
    Date of Patent: December 2, 1986
    Assignee: NEC
    Inventor: Hiroshi Shimizu
  • Patent number: 4626828
    Abstract: In an adaptive encoder encoding an encoder input signal into an encoder output signal by carrying out adaptive prediction, an encoder calculation circuit calculates electric power of an encoder electric signal related to the encoder input signal and the encoder output signal. The adaptive prediction is interrupted by an encoder interruption circuit when the electric power is not greater than a reference electric power. The electric signal may be either the encoder input signal or the encoder output signal. Preferably, a local decoded signal is monitored as the encoder electric signal by the encoder calculation circuit. When adaptive quantization is carried out in the encoder, an adaptive step size may be given as the electric signal to the encoder calculation circuit. An adaptive decoder comprises a decoder calculation circuit for calculating electric power of a decoder electric signal related to either a decoder input signal or a decoder output signal in a manner similar to the encoder calculation circuit.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: December 2, 1986
    Assignee: NEC
    Inventor: Takao Nishitani
  • Patent number: 4622674
    Abstract: A single longitudinal mode semiconductor laser having a distributed Bragg reflector with increased diffractive efficiency. The increased diffractive efficiency results from placing the diffraction grating within the optical waveguide, rather than on either its upper or its lower face. This placement enables maximization of the electric field component of light beams subjected to periodic variations in the refractive index within the optical waveguide, in turn enabling increased reflecting power which results in a low oscillation threshold and a high differential quantum efficiency.
    Type: Grant
    Filed: May 7, 1984
    Date of Patent: November 11, 1986
    Assignee: NEC
    Inventor: Ikuo Mito
  • Patent number: 4620298
    Abstract: An output circuit which can operate at a high-speed is disclosed. The output circuit comprises a series circuit of first and second transistors constituted in a push-pull structure, a third transistor coupled between the control electrodes of the first and second transistors, and control means for making the third transistor conducting prior to establishment of logic states at the control electrodes of the first and second transistors.
    Type: Grant
    Filed: December 14, 1983
    Date of Patent: October 28, 1986
    Assignee: NEC
    Inventor: Takashi Ozawa
  • Patent number: 4596978
    Abstract: A parallel comparison type A/D converter which can produce a digital output with improved monotonic operation.The A/D converter comprises a plurality of comparators for comparing an analog signal with a plurality comparison voltage, and a plurality of logic gates each having a first input terminal of a positive logic and a second input terminal of a negative logic, one of the first and second input terminals receiving an outpt signal from one of the comparators of a certain weight and the other of the first and second input terminals receiving an output signal from the comparator having a weight subsequent to the certain weight. The threshold values of the first and second input terminals are made different from each other.
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: June 24, 1986
    Assignee: NEC
    Inventor: Tsuneo Fujita