Abstract: A telecommunication network which includes a SONET-based digital subscriber loop carrier system that supports wideband and narrowband services. The digital subscriber loop carrier system includes a common module for performing common functions of the system and for transferring subscriber data between the system and a central office or local digital switch, and at least one service definition module, which is coupled to subscribers, for interfacing the subscribers to the system. The common module and the service definition modules are coupled by a common backplane including pulse coded modulation buses and all data, including both subscriber data and control data, are transferred per the SONET protocol. Each of the common module and service definition modules employ buses, which are also based on the SONET protocol.

Abstract: A Feature Interaction Arbitrator (FIA) for identifying the existence of interactions among various telephone call features (e.g., call forwarding busy line and call waiting) and for resolving these interactions. The FIA manages feature interactions in three phases to support a telephone switch as well as a vendor's software development process, the feature administrator of the telephone operating company, feature designer, and for the subscriber (end-user). The first phase is when the feature administrator assigns several features to a subscriber's line. The second phase is when a subscriber activates at least one of the features previously assigned to the subscriber's line. The third phase identifies and resolves feature interactions that occur during run-time operation. During the latter two phases, the FIA is located in the telephone switching system. The FIA provides a database which includes numerical data assigned to classes of feature elements which uniquely define the properties of each feature.

Abstract: An AC current limiter, which is connected in series with a transmission line and which operates in two modes, a conductive mode and a protective mode, includes first and second transistors coupled in parallel with first and second diodes, respectively and the emitters of the first and second transistors serially coupled by a sensing element. First and second gain control networks are couple to the first and second transistors, respectively, to permit control of the gain in the first and second transistors. More particularly, as line current increases to a limiting value, the circuit operates in the protective mode. The voltage across the sensing causes a transistor in one of the first and second networks to turn on, thus diverting current from the respective first and second transistors connected in series with the transmission line. Therefore, line current is limited to a predetermined value.

Abstract: An adaptive clock duty cycle controller which generates a dc error signal that is supplied to a logic device, such as a logic inverter or a logic buffer, which outputs a specified duty cycle clock signal. The output of the logic device is supplied to a positive peak detector, a negative peak detector and an average signal level detector. The output of the positive peak detector and the negative peak detector are supplied to a mid-peak generating circuit which generates a signal for setting and maintaining the desired duty cycle. The signal output by the average signal level detector represents the average value of the output of the logic device. The signal output by the mid-peak generating circuit is compared with the signal output by the average signal level detector by an operational amplifier. The output of the operational amplifier represents the error signal which is supplied back to the input of the logic device to control the output of the logic device to the desired duty cycle.

Abstract: A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling either a direct digital synthesis circuit that provides a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. To minimize jitter and buffer spills (i.e., data overruns or underruns), the frequency and phase of the desynchronized clock is constantly varied to match the variations of the data rate of incoming SONET data. The DDS circuit generates the desynchronized clock, which has a center frequency equal to a predetermined frequency of a reference clock, whose phase is advanced or retarded in accordance with the magnitude of a tuning word supplied by a controller, which implements either a linear, non-linear, or fuzzy logic control algorithm.

Abstract: A low frequency high voltage AC power for a telephone system is provided by a ring signal generator, which produces a ring signal from a DC power supply using a pair of switches controlled by pulse width modulation (PWM) circuit. The ring signal generator includes a PWM circuit driving a pair of MOSFET transistors via a respective pair of opto-isolators. The output of the MOSFET transistor switches is commonly connected to a low pass filter network. The ring signal generator of the present invention advantageously produces a 65 VRMS ring signal at very high efficiency.

Abstract: A method and digital circuit for decoding and recovering a data clock from an incoming stream of Coded Marked Inversion (CMI) encoded data. The CMI encoded data is applied to a shift register where the data is sampled at a rate greater than the incoming transfer rate thus providing multiple samples per data period. The multiple samples having a high logical value occuring during the first half of a data period are counted and a represented value is outputted. The multiple samples having a high logical value occurring during the second half of the data period are also counted and a second represented value is outputted. The two represented values are compared and a single CMI-decoded data bit is determined. The multiple samples are also compared to detect a high-to-low transition which, according to the CMI format, constitutes a data boundary. First and second free-running counters are provided, whose most significant output bits provide an initial clock signal and a recovered data clock, respectively.

Abstract: Many electronic systems such as telephone systems require highly accurate DC-to-AC signal generators such as sine wave generators. A sine wave generator according to the present invention includes a pair of multiplexers, each receiving a plurality of DC voltages from a voltage divider network and having a common output in a summing circuit to produce a sine wave at a predetermined frequency. The multiplexers are controlled by a single up/down counter element which drives the multiplexers to produce identical waveforms in each of the four quadrants of the sine wave. The sine wave frequency can be controlled by controlling a signal provided to the up/down counter.

Abstract: A multiplexing communications system comprising a first terminal means for transmitting and receiving user digitized data, a second terminal means for transmitting and receiving the user digitized data, and a communications link means for conveying the user digitized data in either direction between the first terminal means and the second terminal means. The first terminal means maintains a copy of digital control data which is necessary for controlling the second terminal means. The first terminal means has first download means for transmitting this digital control data to the second terminal means via the communications link means. The second terminal means contains a memory means for storing the digital control data, and control means for controlling the second terminal means during its normal transmitting and receiving operations. The control means requires that the digital control data be accessible from the memory means.

Abstract: A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.