Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.

Abstract: A method of producing a transistor having a source and drain diffusion layer formed so that is has a junction of a shallow depth and is low in parasitic resistance and parasitic capacitance. The method allows the manufacture of a transistor having a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode formed on the gate insulator, and source and drain diffusion layers of one conductivity type formed on the principal plane of the semiconductor substrate across the gate electrode. A semiconductor thin film layer doped with an impurity of the same conductivity type is selectively deposited on the principal plane of the semiconductor substrate on which the source and drain diffusion layers are formed. A facet face is formed at an end portion of the semiconductor thin film which opposes to a sidewall of the gate electrode. The facet face has an inclination angle between a sidewall face of the gate electrode and the principal plane of the semiconductor substrate.

Abstract: Testing elements are disposed to prevent breakage by locating them such that their entire lower surface is formed directly on an insulating layer of a semiconductor device. These testing elements may be used with a fin type storage node electrode projecting from an inter-level insulating layer so as to use the top, side and back surfaces thereof for accumulation of electric charge. These testing elements may be used for evaluating properties of the layers of the storage node electrode and be concurrently formed directly on the inter-level insulating layer, thereby preventing the testing elements from undesirable breakage.

Abstract: An antenna support fabric including an arm (10), a support table (20), a fixing plate (60) which is rotatably secured to the support table (20), a reflection mirror (50) which is detachably fixed to one surface of the fixing plate (60), a primary radiator (40) which is detachably fixed to one surface of the fixing plate (60) through a through hole (51) provided to the reflection mirror (50), and a transceiver (30) which is detachably fixed to the other surface of the fixing plate (60), and engaged with and connected to a projecting portion (41) of the primary radiator (40) through a through hole (62) of the fixing plate (60).

Abstract: Disclosed is a method of restoring data in a non-volatile semiconductor memory which has a memory cell array that a plurality of electrically programmable memory cells to be set of several threshold voltages are matrix-disposed, a data erasing means that divides the memory cell array into several blocks and erases in the lump data stored in memory cells included in the divided block, a data writing means that writes data into the memory cells, a data reading means that reads out data from the memory cells, and a control means that controls the operations of the data erasing means, data writing means and data reading means, wherein the non-volatile semiconductor memory has a function that detects the deterioration of data stored in the memory cells and then restores it, the method having the steps of: detecting the data-deterioration state of memory cells included in the block; conducting a light erasing operation with a threshold voltage change smaller than that of an ordinary erasing operation to an erase bl

Abstract: A speech recognition system, in which partial reference patterns, and cumulative similarities of these patterns, are stored in a temporary pattern memory. The partial reference patterns are to be used as subjects of a similarity computation with an input speech pattern that has its feature quantities extracted by a speech analyzing unit. A counting unit counts partial reference patterns having corresponding cumulative similarities that are higher than a threshold value stored in a threshold memory. A threshold computing unit computes a threshold of pruning from a correspondence relation between the number of partial reference patterns that have corresponding cumulative similarities that exceed the threshold, and the threshold. A similarity computing unit computes a similarity, with respect to the feature quantities, of partial reference patterns with corresponding cumulative similarities that are greater than the threshold of pruning.

Abstract: A method of making a semiconductor device with a shallow (on the order of 50 nm) PN junction depth includes the steps of forming, on a region of a semiconductor substrate in which an impurity diffusion region having the shallow PN junction depth is to be formed, a selectively grown silicon layer (raised layer) containing a substance such as carbon which easily combines with point defects in the semiconductor substrate or a substance such as nitrogen which prevents an impurity providing an electrical conductivity from diffusing, ion-implanting an impurity of one conductivity type into the selectively grown silicon layer, and forming the diffusion region by activating the implanted impurity of one conductivity type and diffusing the impurity of one conductivity type into the semiconductor substrate, by means of heat treatment.

Abstract: By segmenting an image sensing area into a plurality of partial areas and changing the number of stages of dummy vertical electrodes to be inserted between vertical CCD registers and horizontal CCD registers, the output gate electrode, floating diffusion layer, reset gate electrode and rest drain of each horizontal CCD register can be aligned in a line to the main body of the horizontal CCD register. It is therefore possible to avoid the reduction of the transfer efficiency at the time of transferring charges, which have reached the channel under the horizontal transfer electrode, to the channel under a dummy horizontal transfer electrode.

Abstract: There is disclosed a method for controlling the position of a mobile host in a local area network (LAN), whereby the movement of the mobile host out of a certain LAN can be quickly detected even when the mobile host transmits no frames and invalid traffic can be reduced. A server 3 duplicates a learning function table in a bridge device 2 at each specified time. Location confirmation is performed for the currently connected mobile host based on this duplicated information at each specified time. If the mobile host gives no response to the location confirmation, the movement of this mobile host is determined and the learning function table in the bridge device 2 is renewed. Thus, even when the mobile host is moved out of the LAN and no frames are transmitted therefrom, the movement of the mobile host can be quickly detected and invalid traffic can be reduced.

Abstract: Cathode and anode sides of a plurality of solid electrolytic capacitors are connected by simultaneous electric welding. The welding step is effected to connect an anode lead of a lead frame to the anode electrode of a capacitor body and simultaneously connect a cathode lead of the lead frame to the cathode conductor layer of an adjacent capacitor body. The welding electrode for the cathode lead exerts moderate force to the capacitor bodies using a spring function of the capacitor lead. The simultaneous welding for the adjacent capacitor bodies and the moderate force prevent electrical and mechanical damages of the insulator layer of the solid electrolytic capacitors during the welding.

Abstract: A transmission space diversity method which is effective also for a communication system wherein different carrier frequencies are used for transmission and reception is disclosed. Such reception space diversity control that a controlling signal from terminal station 10 is received by two antennas 1 and 2 and receivers 3 and 4 of a base station and the two received controlling signals are compared with each other by reception space diversity controlling signal generation circuit 6 and then that signal which exhibits a higher reception level is provided to switch circuit 8. Furthermore, the reception space diversity controlling signal is utilized for transmission space diversity control of antenna selection wherein the output of transmitter 5 is emitted by one of the antennas.

Abstract: An AC/DC converter of the present invention includes a transformer implemented by a piezoelectric transformer. Power fed from a commercially available power source (14) is converted to a DC voltage by rectification and smoothing. The DC voltage is transformed to a high frequency (about 100 kHz) pulse voltage by switching FETs (Field Effect Transistors) (5) and (6). The pulse voltage is applied to the input of a piezoelectric transformer (9). The transformer (9) has its vibration mode and dimension selected such that the resonance frequency of the transformer is substantially identical with the frequency of the above pulse wave. A high frequency AC voltage is produced from the output side of the transformer (9). The AC voltage is transformed to a DC voltage by rectification and smoothing and then fed to a load resistor (13). The piezoelectric transformer is easy to miniaturize, compared to an electromagnetic transformer. The entire AC/DC converter can therefore be reduced in size.

Abstract: An electrostatic ink-jet recording head (100) with an ink chamber (15) for storing ink containing electrified toner; an ink path (6) leading to the ink chamber; ink ejecting portions (7, 8) provided at the tip of that ink path; electrophoretic electrodes (15, 11, 11') for moving the electrified toner of the ink along the ink path to the ink ejecting portions by electrostatic repulsive force; and a plurality of ejecting electrodes (2a-2h) , arranged near the ink ejecting portions, for forming an electric field for providing an ejecting force to the electrified toner. The ejecting electrodes are controlled by ejection control electrodes (3a, 3b) that form an electric field for preventing electrified toner from being ejected from the ink ejecting portions. The plurality of ejecting electrodes (2a-2h) are formed along the ink path, and the ejecting electrodes and ejection control electrodes are stacked over a substrate with insulating layers therebetween.

Abstract: A digital phase locked loop (PLL) comprises a phase/frequency comparator block including a comparator for comparing a reference signal with an internal clock signal obtained by dividing an output clock signal of the PLL circuit. The phase/frequency comparator supplies a two-bit signal, either one of the bits having a pulse width based on the difference between the phases or frequencies of the reference signal and internal clock signal. The two-bit signal is amplified by a CMOS latch amplifier during a sense enable cycle of the amplifier to be supplied to a digital controller, which in turn controls a voltage controlled oscillator via a D/A converter. The digital PLL circuit executes frequency acquisition and phase acquisition in a single mode to simplify the circuit configuration.

Abstract: A decode circuit for use in a semiconductor memory device can prevent an increase of an area of X-decoder and can possess a plurality of banks with operating speed maintained. A word line selection signal makes a word line of a first bank region high level, before it makes first bank selection measure "off" to separate word line selection measure from the first bank region. Next, it makes second bank selection measure "on" to use the word line selection measure for selecting the word line of the second bank region so that one word line selection measure is used in common in terms of both the first bank region and the second bank region.

Abstract: The non-volatile semiconductor memory of the present invention comprises a memory cell transistor to which three or more threshold values are set by controlling the floating gate-source voltage, wherein the voltage of the floating gate is maintained constant while the voltage applied to the source is varied.

Abstract: A plurality of antennas receives radio wave transmitted from a vehicle which comes in a toll collection area. Each antenna has at least three antenna elements, and the antennas are disposed in the horizontal direction and vertical direction. The signal analyzer analyzes the ID signal included in the received radio wave to identify the vehicle. The direction detector measures the direction of arrival (DOA) of radio wave received by two antennas selected by the antenna selector by way of two-dimensional interferometry principle in terms of the directional angle and depression angle. The location detector calculates the location of the vehicle in the horizontal direction and the height in the vertical direction of the vehicle as a location information based on the DOA of the radio wave measured by the direction detector.

Abstract: A communication device for use in a base station of a portable telephone system has a radiation section including a spiral projection formed on an external surface of a casing to define a spiral air passage on the casing, a fan disposed on the casing inside a central space of the spiral passage, and a motor disposed inside the casing to drive the fan through a shaft penetrating the wall of the casing. A spiral air flow generated by the fan functions for efficient heat radiation through the casing. The spiral projection is formed by drawing the wall of the casing.

Abstract: In a video analysis device, a frame separator separates from frame images respresentative of a moving object at least first and second key frames based on either a scene change or a great movement of the object. Responsive to color and edge information, a region divider divides each key frame into region data. A vector detector applies block matching to the key frames to detect block motion vectors and detects in response to the region data of the first key frame a plurality of region motion vectors. Responsive to the region data and the region motion vectors, a correspondence establishing unit establishes correspondence between one of the region data of the first key frame and the region data of the second key frame to identify the object.

Abstract: The present invention is a digital-to-analog converter comprising: a core digital-to-analog converter which converts digital signal of first number of bits to analog signal, a generator of an addend whose duty corresponds to the digital signal of second number of bits, an adder which adds the addend as least significant bit to the digital signal of first number of bits and supplies its output to the core digital-to-analog converter, and a filter which is supplied with its input from the core digital-to-analog converter and eliminates the ripples of the input to provide a ripple-eliminated analog signal at its output terminal, whereby the digital-to-analog converter can converts a digital signal of number of bits which exceed the first number, more exactly is the sum of the first number and the second number, to an analog signal.