Patents Assigned to NEC Corporation
  • Patent number: 5971608
    Abstract: An apparatus for inspecting bump junctions in a semiconductor flip chip mounting which is able to inspect a state of a junction portion, has a simple structure and is safe and suitable for mass production of semiconductor devices and a method of inspecting the same; in an apparatus for inspecting bump junction in semiconductor flip chip mounting in which a semiconductor bare chip is mounted reversely on a substrate through the bumps, the surface of the semiconductor bare chip is irradiated with a laser light and radiation heat from the heated chip is detected with an infrared camera, a computer acquires temperature distribution on the chip surface from a picture processing unit and analyzes the temperature distribution, thereby to decide the quality of the bump junction state, and decision processing is performed by acquiring data of temperature distribution from a reference semiconductor device of known excellent quality in advance by the same method and comparing with these data.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Takao Koizumi
  • Patent number: 5973551
    Abstract: A detection circuit detects an abnormal current which flows through a first output transistor. In this event, the first output transistor is connected to an external power supply via a load resistor. The above detection circuit mainly includes a second transistor, a constant current supply, a third transistor, a fourth transistor, and a comparator circuit. The constant current supply supplies a constant current into the second transistor. Further, the third transistor is connected to the first output transistor and performs an ON-OFF operation in synchronism with the first output transistor. On the other hand, the fourth transistor is connected to the third transistor in serial and performs the ON-OFF operation opposite to the first output transistor. Moreover, the comparator circuit has a first input and a second input.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Mitsuda
  • Patent number: 5973881
    Abstract: An air bearing magnetic head slider includes a slider body carrying a preselected write/read device thereon. A preselected air stream flows in the vicinity of one major surface of the slider body during operation. At least a pair of side rails are formed on the major surface of the slider body and extend along the air stream. A cross rail connects the air inlet ends of the side rails. The side rails each is formed with preselected grooves each of which is delimited by the bottom wall substantially parallel to the major surface of the slider body and side walls connecting the bottom wall and the surface of the side rail. The bottom wall and each side wall are inclined by an angle of less than 90 degrees relative to each other.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Ken Ajiki
  • Patent number: 5974555
    Abstract: A pipeline processing apparatus having reduced power consumption including a plurality of serially connected stages, a plurality of clock signals different in phase from each other supplied to the stages individually. The clock signals can be stopped independently, so as to limit power consumption.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Takashi Nakayama
  • Patent number: 5974575
    Abstract: The simulation device and method exhaustively checks for the influence of skew in external input signals caused by numerous instances of unspecified tester skew to prevent testing problems when testing ICs such as ASIC before shipment. The simulation device is provided with a sequential circuit detection processor 1 that detects all first-stage sequential circuit elements 17 that may be affected by tester skew and outputs sequential circuit element information, a skew value library 4 for simulation use to which is added tester skew value fluctuation, and a data substitution section 3 that directs operation execution to an arithmetic section 6, transcribes prescribed data of the skew value library 4 to a normal library 5, and substitutes data of a net list 7.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Kiyoshi Fujimoto
  • Patent number: 5972739
    Abstract: A resin-encapsulated semiconductor device includes a semiconductor chip consisting of a semiconductor element having metal bumps and metal leads electrically connected to the metal bumps and having a surface-treated layer obtained by a surface treatment, and a resin film stacked on the outer side of the semiconductor chip and tightly adhered to the semiconductor chip by a heat treatment and pressurization treatment.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Yoshitsugu Funada, Koji Matsui
  • Patent number: 5974163
    Abstract: In order to classify fingerprint images with a high precision by integrating classification results and their merits of different classification means making use of their probability data, a fingerprint image classification system of the invention includes: a plurality of classification units (12 and 15), each of the plurality of classification units (12 and 15) generating an individual probability data set (17 or 18) indicating each probability of a fingerprint image (16) to be classified into each of categories; a probability estimation unit (13) for estimating an integrated probability data set (19) from every of the individual probability data set (17 and 18); and a category decision unit (14) for outputting a classification result of the fingerprint image (16) according to the integrated probability data set (19).
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: October 26, 1999
    Assignee: Nec Corporation
    Inventor: Toshio Kamei
  • Patent number: 5968589
    Abstract: A wiring pattern is selectively formed on a base member by permanent resist. Furthermore, the thickness of a non-electrolytic copper plating layer is made thinner than that of a permanent resist layer on the base member, so that a concave shape is formed in combination with the permanent resist layer. A solder resist layer is formed on the non-electrolytic copper plating layer and the permanent resist layer except for a pad portion formed by the non-electrolytic copper plating layer, and a peripheral portion of the pad portion is surrounded by a wall formed by the permanent resist layer and the solder resist layer. Solder is supplied onto the pad portion surrounded by the wall by way of either the MICROPRESS method or the MICROBALL method.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Tomoo Murakami
  • Patent number: 5968195
    Abstract: In a failure section estimating apparatus for a sequential circuit, when it is determined that the failure section is positioned in the current stage combination circuit, an input vector estimating section estimates input vectors each of which sets to a failure state, at least a predetermined output section as a failure output section of an output boundary of a current stage combination circuit of the sequential circuit. A failure output propagation path determining section determines a failure output propagation region in the current stage combination circuit for each of the estimated input vectors to be applied to an input boundary of the current stage combination circuit. The failure output propagation region represents connection paths between the failure output section and input sections of the input boundary to which the failure output section is indirectly connected.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Toshio Ishiyama
  • Patent number: 5969635
    Abstract: In the radio paging receiver having an announcing arrangement for announcing reception of a radio call signal, an operable switch (16) is provided for determining a particular mode relating to an operation of the announcing arrangement. Received with the radio call signal, a receiving arrangement produces a received signal. In accordance with a state of the operable switch and with a form of the received signal, a control section (17) controls the operation of the announcing arrangement. It is preferable that the control section inhibits the operation of the announcing arrangement when a massage is absent in the radio call signal.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Kazuhumi Goto
  • Patent number: 5970366
    Abstract: In a method of forming a silicon substrate, a gettering film is formed on a bottom surface of a silicon substrate. An oxygen ion implantation into a top surface of the silicon substrate is carried out at a substrate temperature in the range of 400.degree. C.-700.degree. C. The gettering film is removed from the silicon substrate. The silicon substrate is subjected to a heat treatment at a temperature of not less than 1300.degree. C. for causing a reaction of oxygen and silicon to form a silicon oxide film in the silicon substrate after the gettering film is removed.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Kensuke Okonogi
  • Patent number: 5969512
    Abstract: The output of the power unit 21 varies on the basis of the output of the power unit 22, and temperature-compensated in accordance with an ambient temperature. The control is performed by the output voltage control circuit 3. The output voltage of the power unit 21 is varied with an output voltage ratio between the outputs of the power units, and by compensating an output voltage of the power unit 22 in accordance with the ambient temperature, the output voltage of the other power unit 21 can be temperature-compensated by the control circuit 3.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Hirotsugu Matsuyama
  • Patent number: 5970334
    Abstract: In a method of manufacturing a semiconductor device having a first conductive layer of a first conductive type and a second conductive layer of a second conductive type opposite to the first conductive type, an intermediate layer of a predetermined element selected from the group V is formed on the first and second conductive layers to a preselected thickness of several atomic layers. Next, a metal film is deposited on the intermediate film. The intermediate layer is absorbed in the metal film and vanishes during the deposition of the metal film. The metal film may be formed of tungsten or molybdenum, while the thickness of the intermediate layer may be equal to one or two atomic layers.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Hiroshi Tsuda
  • Patent number: 5969467
    Abstract: A field emission cathode includes a first electron-emitting structure having a first cathode electrode (3), a first gate electrode (5), a first insulating layer (4) separating the first cathode electrode (3) from the first gate electrode (5), and at least one first emitter tip (9) disposed in a hole formed in the first gate electrode (5) and the first insulating layer (4) to expose a portion of the first cathode electrode (3); and a second electron-emitting structure surrounding and insulated from the first electron-emitting structure wherein the second electron-emitting structure has a second cathode electrode (6), a second gate electrode (8), a second insulating layer (7) separating the second cathode electrode (6) from the second gate electrode (8), and at least one second emitter tip (10) disposed in a hole formed in the second gate electrode (8) and the second insulating layer (7) to expose a portion of the second cathode electrode (6).
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Fumihiko Matsuno
  • Patent number: 5970287
    Abstract: A low-cost non-contact type charging device having excellent uniform charging performance and long stable charging characteristic includes an insulating support body having an insulating surface, first electrodes, to which a first voltage is applied, and second electrodes, to which a second voltage is applied. The first electrodes and the second electrodes, isolated from each other, are alternately formed, in non-parallel to a relative moving direction between a charging member and a charged body. Further, the first electrodes and the second electrodes are provided at respective positions in a width in the relative moving direction of the charging member, and moved close to the charged body in a non-contact state.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Chiseki Yamaguchi
  • Patent number: 5969577
    Abstract: A voltage controlled oscillator is implemented by odd inverters forming a loop, and a depletion type load transistor, a depletion type frequency control transistor and a depletion type compensating transistor supply driving current to an enhancement type driving transistor in each inverter; the compensating transistor is controlled by a reference voltage generator implemented by a series of resistor and a depletion type load transistor, and fluctuation in a fabrication process equally affects the depletion type transistors; when the depletion transistors increases the driving current, the resistor decreases the reference voltage supplied to the gate electrode of the depletion type compensating transistor, and the depletion type compensating transistor cancels the increment of the driving current so as to make the voltage controlled oscillator less sensitive to the fluctuation of the threshold.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Makoto Kaneko
  • Patent number: 5969401
    Abstract: The present invention provides a silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to the first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between the first and second silicon substrate, so that the first and second silicon substrates on the plurality of first type regions are indirectly bonded through the plurality of insulation film patterns while the first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein each of the plurality of first type regions is bounded on all sides by the plurality of second type regions while each of the plurality of second type regions is bounded on all sides by the plurality of first type regions.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Tomohiro Hamajima
  • Patent number: 5968441
    Abstract: A laser processing method for ablating a transparent material is disclosed. A laser beam absorption layer is formed in a desired ablation portion beforehand by the implantation of an impurity or the increase of a defect density. The absorption layer obviates damage ascribable to thermal strain and, when use is made of a VUV (Vacuum Ultra Violet) beam, damage to portions other than an irradiated portion. This allows a simple apparatus to implement the ablation of a transparent film.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: October 19, 1999
    Assignee: Nec Corporation
    Inventor: Yuko Seki
  • Patent number: 5970396
    Abstract: A diversity receiver having a pair of receiving circuits, which is capable of disconnecting a faulty receiving circuit from its operation for preventing a communication quality from being degraded due to mis-selection of output signal of the faulty receiving circuit in a case of signal level being received is too low to discriminate between output signals of the faulty receiving circuit and the normal receiving circuit, is provided. The diversity receiver includes a first and second error rate accumulation circuits, each is coupled with corresponding receiver circuit, to accumulate error rate of each receiver circuit in a timing generated by a timing generator circuit. In combination of six judge circuits, first judge circuit to sixth judge circuits, and input of error accumulation value of each receiving circuit, it is judged whether or not there exist a fault in a receiving circuit and which receiving circuit is faulty.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventor: Katsunori Takashima
  • Patent number: 5969781
    Abstract: An LCD (Liquid Crystal Display) of the present invention includes a pair of substrates facing each other and at least one of which is transparent. A liquid crystal composition intervenes between the substrates. Scanning wirings and signal wirings are arranged on one substrate in a matrix configuration. Pixel electrodes each constitutes one pixel. Switching devices each is positioned at a portion where one of the scanning wirings and one of the signal wirings intersect each other, for controlling the application of a voltage to the associated pixel electrode. Common electrodes are formed on the other substrate. The liquid crystal composition has positive dielectric constant anisotropy and is oriented vertically to the facing surfaces of the substrates when a voltage is not applied. The common electrodes are parallel to the pixel electrodes and positioned at both sides of said pixel electrodes.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventors: Hiroaki Matsuyama, Shinichi Nishida