Patents Assigned to NEC
  • Patent number: 7502613
    Abstract: A cellular phone includes a random number generator. When the cellular phone performs location registration operation, a time of executing location registration is determined by random numbers. Therefore, in a situation where a large number of cellular phones must perform location registration substantially simultaneously, an event where a large number of the location registration operations overlap with one another can be avoided. Hence, simultaneous concentration of loads on a network is eliminated, and stable communications between the cellular phones and an administrative server are maintained.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: March 10, 2009
    Assignee: NEC Corporation
    Inventors: Hideo Namiki, Yoshiaki Oomori
  • Patent number: 7501584
    Abstract: A structure for connecting substrates to each other, which is capable of thinning an electronic device on which a plurality of circuit boards is mounted, saving a space of the electronic device, and detaching a circuit board from the electronic device. The circuit board unit includes a first substrate including, on a surface thereof, a first group of electrode terminals arranged in a matrix, a second substrate including, on a surface thereof, a second group of electrode terminals arranged in a matrix in alignment with the first group of electrode terminals, and an anisotropic electrical conductor sandwiched between the first and second substrates. The first and second substrates and the anisotropic electrical conductor are pressurized by means of a pressurizer to electrically connect the electrode terminals to each other through the anisotropic electrical conductor.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 10, 2009
    Assignee: NEC Corporation
    Inventors: Yoshiyuki Hashimoto, Junya Sato
  • Patent number: 7501317
    Abstract: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Matsuda, Hiroshi Kitajima
  • Patent number: 7501707
    Abstract: The semiconductor apparatus includes an upper semiconductor chip having an upper external terminal and a lower semiconductor chip having a lower bump for electrically connecting a lower external terminal and the upper external terminal. The circuit surfaces of the upper semiconductor chip and the lower semiconductor chip are electrically connected to each other via the bump. A low impedance line having lower impedance than the internal line of the lower semiconductor chip is formed on top of the lower semiconductor chip for electrically connecting the lower external terminal and the bump.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoshiaki Morishita, Nobuteru Oh
  • Patent number: 7501716
    Abstract: A power supply apparatus that output two types of power supply includes a first series regulator for outputting power supply to a first power supply line, a second series regulator for outputting power supply to a second power supply line, an OR circuit for outputting High level signal to activate the first series regulator upon when detecting presence of either one of output from the second series regulator and an activation command by an ON/OFF control signal, and an AND circuit for outputting High level signal to activate the second series regulator when detecting presence of both of output from the first series regulator and an activation command by the ON/OFF control signal.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shigeto Nakajima
  • Patent number: 7502378
    Abstract: A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: March 10, 2009
    Assignee: NEC Laboratories America, Inc.
    Inventors: Marcello Lajolo, Subhek Garg
  • Patent number: 7502018
    Abstract: An electronic whiteboard system has light emitting elements mounted on ultrasonic wave receivers of a signal processor, and an imager device for imaging the light emitting elements and a projection test pattern of a projector to acquire a positional relationship between the light emitting elements and an image projected from the projector. The electronic whiteboard system can facilitate initialization of the coordinates with the acquired positional relationship.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: March 10, 2009
    Assignee: NEC Display Solutions Ltd.
    Inventor: Youichi Tamura
  • Publication number: 20090058306
    Abstract: The light-guide plate has an extended portion. The extended portion has a recess formed in a thickness direction, and the optical sensor is arranged within the recess.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventor: Hideki ITAYA
  • Publication number: 20090060064
    Abstract: An OFDM communication system which performs appropriate feedback flexibly adapted to channel states, while suppressing an amount of feedback information. The OFDM communication system has first and second communication apparatuses. In a second receiver of the second communication apparatus, a channel quality measurement part measures channel quality for each of sub-carriers. A time variation measurement part and a frequency measurement part respectively measure variation of channel quality in a time domain and a frequency domain, respectively, and output the variation of channel quality as time variation information and frequency variation information, also respectively. Based on the measured time variation information and frequency variation information, a two-dimensional control part performs two-dimensional blocking for forming two-dimensional blocks each from plural adjacent sub-carriers which are adjacent to each other in the time domain and the frequency domain.
    Type: Application
    Filed: April 4, 2006
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventors: Hisashi Futaki, Yoshikazu Kakura, Shousei Yoshida, Takumi Ito
  • Publication number: 20090059928
    Abstract: Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventors: Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Youichi Hidaka, Jun Suzuki, Takashi Yoshikawa
  • Publication number: 20090063727
    Abstract: A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 5, 2009
    Applicant: NEC Corporation
    Inventors: Nobutatsu NAKAMURA, Koji Kida, Kenichiro Fujiyama
  • Publication number: 20090060059
    Abstract: The accuracy of time information set in a packet is improved. Time information calculator 24 calculates time information, using the encoding information received by control information receiver 23 and the encoded stream received by encoded stream receiver 21. When the time information is not pertinent, time information calculator 24 corrects the time information and outputs the corrected time information. Encoded stream packetizer 22 packetizes the encoded stream by setting the time information output by time information calculator 24 into the header portion.
    Type: Application
    Filed: January 17, 2007
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventors: Kazuhiro Koyama, Kazunori Ozawa
  • Publication number: 20090064110
    Abstract: A system and method for mining program specifications includes generating unit tests to exercise functions of a library through an application program interface (API), based upon an (API) signature. A response to the unit tests is determined to generate a transaction in accordance with a target behavior. The transaction is converted into a relational form, and specifications of the library are learned using an inductive logic programming tool from the relational form of the transaction.
    Type: Application
    Filed: March 18, 2008
    Publication date: March 5, 2009
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: SRIRAM SANKARANARAYANAN, FRANJO IVANCIC, AARTI GUPTA
  • Publication number: 20090063808
    Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.
    Type: Application
    Filed: August 7, 2008
    Publication date: March 5, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Hideki Matsuyama, Masayuki Daitou
  • Publication number: 20090058384
    Abstract: A reference voltage generating circuit includes a constant current source circuit connected with a power supply voltage and configured to output a reference current to an output node based on the power supply voltage. A current-voltage converting circuit is connected the output node and generates a reference voltage to the output node based on the reference current. A first voltage adjusting circuit is connected with the output node and is configured to adjust dependence of the reference voltage on the power supply voltage in a positive direction. A second voltage adjusting circuit is connected with the output node and is configured to adjust dependence of the reference voltage on the power supply voltage in a negative direction.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kazutaka Taniguchi
  • Publication number: 20090059107
    Abstract: A transflective LCD unit includes an array of pixels each including a reflective area and a transmissive area. The LC layer has an effective retardation of ?/4 in the reflective area, and an effective retardation of ?/2 in the transmissive area. A retardation film disposed in the reflective area provides a retardation of ?/2 to the light passed thereby. An angle of ? between the optical axis of the retardation film and the polarized direction of the light is in a range of 0 degree<?<22.5 degrees.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 5, 2009
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Hiroshi NAGAI, Michiaki SAKAMOTO, Kenichi MORI, Kenichirou NAKA
  • Publication number: 20090057787
    Abstract: There is provided a semiconductor device which can control a reaction caused between a gate electrode and a high-k gate dielectric film, and which has an element structure suitable for higher integration and speed-up. The semiconductor device has an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor has: a gate insulating film including a high-k dielectric film; and a gate electrode with a laminated structure including a first conductive layer, and a second conductive layer which has a resistivity lower than that of the first conductive layer, and the first conductive layer is provided on and in contact with the high-k dielectric film, and includes titanium nitride with a density of 5 g/cm3 or more.
    Type: Application
    Filed: September 2, 2008
    Publication date: March 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takeo MATSUKI, Kazuyoshi TORII
  • Publication number: 20090059944
    Abstract: A distributed processing system includes a first information processing device, two or more second information processing devices connected with the first information processing device via a first network, and the second information processing devices being connected with each other via a second network, wherein the first information processing device includes an input division unit that generates divided input data pieces by dividing an input data set, and a divided input distribution unit that transmits the divided input data pieces to the second information processing devices, and wherein the second information processing devices include a divided input transfer unit that transmits the divided input data piece to the second information processing device assigned as the base terminal from one or more of the second information processing devices assigned as a client terminal, and a divided input combining unit that combines the divided input data pieces to restore the input data set.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventor: Takayuki OMINO
  • Publication number: 20090059070
    Abstract: Pulse detection portion detects pulses in a horizontal synchronization signal and acquires the occurrence period and the pulse width of the detected pulses. Synchronization pulse decision portion determines pulses, for which the differences between the occurrence period and the reference period and between the pulse width and the reference pulse width are within their respective error tolerance ranges, as synchronization pulses. Mean period acquisition portion obtains the mean period by averaging occurrence periods of the synchronization pulses. Reference period correction portion carries out either or both of correcting the reference period so as to get closer to the mean period and correcting the error tolerance range of the reference period so as to get narrower, under the condition that the occurrence frequency of the synchronization pulses for which the difference between the occurrence period and the mean period is outside of a predetermined tolerance range exceeds a predetermined threshold.
    Type: Application
    Filed: July 14, 2008
    Publication date: March 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takeo Matsui
  • Patent number: D588059
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 10, 2009
    Assignee: NEC Corporation
    Inventors: Yoshihiro Fujita, Manabu Tominaga