Abstract: A method and system are described for canceling far end cross-talk in communication systems. A first transmitter transmits the first effective data source signals across the first channel. A second transmitter transmits the second effective data source signals across the second channel. In one embodiment, a receiver unit receives first and second effective data source signals across a first channel and a second channel, respectively, and also one or more cross-talk signals. A far end cross talk (FEXT) canceller located in the receiver unit receives second estimated effective data source signals based on the second effective data source signals. The receiver unit cancels the one or more cross-talk signals using the second estimated effective data source signals.

Abstract: A method and device that allow picture slices of a Video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: A receiver is optimized by adapting parameters of components within the receiver. Various component parameters are adapted by using either a least means squared algorithm or a steepest descent algorithm. The taps of a decision feedback equalizer can be adapted by using either a least means squared algorithm or a steepest descent algorithm. The gain value of a linear equalizer and the input of a digital to analog converter coupled to the linear equalizer are also adapted through the least means squared algorithm or a steepest descent algorithm. A variable gain amplifier is also capable of being adapted through the use of the least means squared algorithm. Clock offsets are also configured by use of a steepest descent algorithm.

Abstract: An adaptive nonlinear filtering system includes an adaptive filter module that is configured to generate relative location information pertaining to a relative location of an input signal within an input range; determine an input dependent filter parameter based at least in part on the relative location information; generate an output signal based at least in part on the input dependent filter parameter; and feed back a feedback signal that is generated based at least in part on the output signal and a target signal.

Abstract: A signal processing method includes inputting a digital signal, providing a plurality of coefficients; and determining an output. The output is approximately equal to an aggregate of a plurality of linear reference components, and each of the linear reference components is approximately equal to an aggregate of a corresponding set of digital signal samples that is scaled by the plurality of coefficients.

Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.

Abstract: A device for generating a crest factor reduced signal is disclosed. The device comprises an interface for receiving an input signal; a peak identifier for identifying one or more peak regions of the input signal; a squelch level determiner for determining a reduction of the input signal near the one or more peak regions; a squelcher for reducing the one or more peak regions of the input signal as indicated by the squelch level determiner; and an interface for outputting a crest factor reduced signal. The crest factor reduced signal has a reduced dynamic range due to the reduction of the one or more peak regions of the input signal. The crest factor reduced signal also has been filtered to reduce undesired frequency components by: calculating a difference between a squelched signal from the squelcher and the input signal, band-pass filtering the difference to generate a result, and summing the result with the input signal that has been delayed.

Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.

Abstract: A content addressable memory (CAM) device can include a number of bit line. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit can have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state in response to, and no later than the start of, an access operation.

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract: An improved Tomlinson Harashima Precoding (THP) communication system through special configuration of its feedback coefficients is disclosed. Improvement, in terms of THP system robustness against analog-to-digital (ADC) sampling phase variation, is achieved either by deriving feedback coefficients of the Decision Feedback Equalizer at worst ADC sampling phase or by inserting a Zero Edge Filter (ZEF) at the receiver. The ZEF modifies the communication system such that the feedback filter coefficients derived in the Decision Feedback Equalizer (DFE) mode and later used in the THP mode is capable to compensate the zero at Nyquist Frequency due to a non-optimum sampling, phase of the ADC. The THP communication system, modified and improved with the insertion of ZEF, is operable to switch from an adaptive Decision Feedback Equalizer (DFE) mode to a THP mode having an adaptive Linear Equalizer (LE) at the receiver.

Abstract: A content addressable memory (CAM) (100) can include a CAM memory array (102) having both a data field (102-0) and a mask field (102-1). A multiplexer (MUX) (108) can selectively load data from either a register (104) or an external data input (106) to one or both fields (102-0 and 102-1) of CAM memory array (102).

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.

Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at least one signal for each logical block to physical block from a corresponding a set of r+1 physical blocks, each set of r+1 physical blocks being different from one another.

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.