Abstract: A capacitive tuning circuit includes radio frequency (RF) switches connected to an RF line. Each RF switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, and RF terminals having lower metal portions and upper metal portions. Alternatively, the RF terminals can have a trench metal liner separated from a trench metal plug by a dielectric liner. At least one capacitor is formed in part by at least one of the lower metal portions, upper metal portions, or trench metal liner. The capacitive tuning circuit can be set to a desired capacitance value when a first group of the RF switches is in an OFF state and a second group of the RF switches is in an ON state.

Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: Disclosed is a heterojunction bipolar transistor (“HBT”) including an intrinsic base in a SiGe layer. The HBT has a raised germanium extrinsic base over the SiGe layer. A base contact is situated over and contacting the raised germanium extrinsic base. An emitter is situated over the intrinsic base, and a collector is situated under the intrinsic base. The raised germanium extrinsic base has a reduced parasitic base-collector capacitance. The raised germanium extrinsic base is situated between a first dielectric layer and a second dielectric layer. Spacers are situated adjacent the second dielectric layer. The first dielectric layer can be a nitride based dielectric, the second dielectric layer can be an oxide based dielectric, and the spacers can be a nitride based dielectric.

Abstract: Disclosed is a method for fabricating a heterojunction bipolar transistor (“HBT”), and the resulting structure. The method includes forming a germanium layer over a SiGe layer, the SiGe layer including an intrinsic base. Thereafter, an emitter sacrificial post and a raised germanium extrinsic base are formed by etching away portions of the germanium layer. Then, a conformal dielectric layer is deposited over the raised germanium extrinsic base. The process continues by removing the emitter sacrificial post and forming an emitter over the intrinsic base within an emitter opening defined by the previous removal of the emitter sacrificial post. The resulting structure has a raised germanium extrinsic base with a reduced parasitic base-collector capacitance.

Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.

Abstract: Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device.

Abstract: Disclosed is a radio frequency (RF) switch branch having a reduced nonlinearity and an associated method for reducing nonlinearity in a RF switch branch. The RF switch branch includes a primary transistor, a first transistor having power terminals electrically connected between a drain node and a body node of the primary transistor, and a second transistor having power terminals electrically connected between the body node and a source node of the primary transistor. The RF switch may further include a body resistor electrically connected between the body node of the primary transistor and ground, and a gate resistor electrically connected between a gate of the primary transistor and a gate voltage source. A gate of each of the first transistor and the second transistor is electrically connected to the gate voltage source such that the first transistor and the second transistor are ON only when the primary transistor is ON.

Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.

Abstract: Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.

Abstract: Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.

Abstract: Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

Abstract: Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate.

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

Abstract: According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate.

Abstract: A disclosed embodiment is a switching circuit including a number of transistors fabricated in a device layer situated over a buried oxide layer and a bulk semiconductor layer. Each transistor has a source/drain junction that does not contact the buried oxide layer, thus forming a source/drain junction capacitance. The disclosed switching circuit also includes at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thus electrically isolating at least one of the transistors in the switching circuit so as to reduce voltage and current fluctuations in the device layer. The disclosed switching circuit may be coupled to a power amplifier or a low noise amplifier and an antenna in a wireless communications device, and be controlled by a switch control signal in the wireless communications device.

Abstract: A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater.