Abstract: According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap.

Abstract: According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.

Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the second nitride spacer are separated by a distance substantially equal to a critical dimension. For example, the first nitride spacer and the second nitride spacer may comprise LPCVD or RTCVD silicon nitride. According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between said first nitride spacer and said second nitride spacer, where the emitter has a width substantially equal to the critical dimension. The emitter may, for example, comprise polycrystalline silicon. In another embodiment, a method that achieves the above-described heterojunction bipolar transistor is disclosed.

Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: According to one exemplary embodiment, a VCO core circuit is connected across a first node and a second node. The anode of a first varactor is connected to the first node while the anode of a second varactor is connected to the second node, and the cathode of the first varactor is tied to the cathode of the second varactor. A tuning voltage is also connected to the cathode of the first varactor and the cathode of the second varactor. The inductor is connected across the first node and the second node. A first and second bipolar transistors are configured as a differential pair. A first and second FETs are configured in a common-gate configuration. The drain of the first FET comprises a first output of the BiFET VCO circuit, while the drain of the second FET comprises a second output of the BiFET VCO circuit.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor.