Abstract: A receiver arranged to process a flow of data in a communication system for downlink shared channels and a method for processing the flow of data sequence. The receiver includes a processor that receives a subframe comprising a data packet; a demapper that receives supplemental channel data symbols and is positioned after the processor in a sequence of the flow of data; means for performing rate matching of estimated the data symbols and positioned after the demapper in the data sequence; and a Hybrid Automatic Retransmission Request (HARQ) buffer positioned before the demapper in the data sequence. The communication system includes a long-term evolution (LTE) communication system.

Abstract: One embodiment provides a method of performing packet identifier (PID) filtering of a digital video broadcasting-handheld (DVB-H) transport stream and includes processing a PID and a continuity counter (CC) sequence of the DVB-H transport stream, computing a number of mismatched bits between the PID and a desired PID, proceeding to a start of a reset state on a first-in-first-out (FIFO) queue of the DVB-H transport stream when a FIFO buffer becomes full, determining if a number of mismatched bits of a first packet in the FIFO buffer is less than a first threshold value, and proceeding to a start of a run algorithm state only if the number of mismatched bits of the first packet in the FIFO buffer is less than the first threshold value and if there is a valid CC sequence that includes the first packet.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source VSS that indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source VDD that indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Abstract: An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.

Abstract: A portable memory device dimensioned and configured as any of a removable flash memory card, a USB flash drive, and a jump drive and a method of wireless communication, wherein the portable memory device comprises a single housing component; a data storage component within the single housing component; and a wireless receiver operatively connected to the data storage component and within the single housing component, wherein the wireless receiver is adapted to receive wireless signals comprising radio signals, satellite signals, TV signals, and Bluetooth™ specification signals, and wherein the wireless receiver is adapted to wirelessly communicate with a LAN. The portable memory device may further comprise an interface component adapted to connect to a host computing device. Preferably, the TV signals comprise mobile TV signals.

Abstract: A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Abstract: An electrical circuit includes a first transistor having a first source, a first drain, and a first gate, whereby the first transistor receives an input voltage through the first gate. An output voltage terminal outputs voltage from the first transistor and is connected to the first drain. A second transistor includes a second source, a second drain, and a second gate, whereby the second transistor receives a bias voltage through the second gate, and wherein the first source is connected to the second drain. A first capacitor is connected to the first source, the second source, and the second drain. An inductor is connected to the first drain. A second capacitor is connected in parallel with the inductor and further connected to the first drain.

Abstract: A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

Abstract: A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

Abstract: Reducing a frame size in a memory for a receiver includes compressing a first analog television picture frame, storing the compressed frame in the memory, decompressing the compressed frame from the memory, obtaining a second analog television picture frame. The first frame includes a first set of pixels that further include at least one of Red/Green/Blue (RGB) samples and, the second frame includes a second set of pixels. Each of the first set of pixels of first frame being decompressed are compared with the corresponding second set of pixels of second frame to obtain an alpha (?) factor. A Signal to Noise Ratio (SNR) and a motion per pixel of the first set of pixels and the second set of pixels are compared. Each of a pixel is displayed based on the ? factor.

Abstract: Performing real-time compression on an image for target buffer fullness includes dividing the image into N macro-blocks, performing a discrete cosine transformation (DCT) on each of the N macro-blocks, defining a Quantization Parameter Scalar (Q) for each of the N macro-blocks of the image on the DCT being performed, initializing the Quantization Parameter Scalar (Q) for the first Macro-block to a value that correlates to a buffer fullness of a previously compressed image, and monitoring the buffer fullness by comparing the buffer fullness with the target buffer fullness. The N macro-blocks include 16×16 macro-blocks. The Q value is increased to a first new value when the buffer fullness is greater than the target buffer fullness. The Q value is decreased to a second new value when the buffer fullness is less than the target buffer fullness.

Abstract: Color information decoding on a composite video signal that includes modulated color information for an analog television receiver. A first burst locked oscillator (BLO) operates in a first loop gain, and a second BLO operates in second loop gain and is operatively connected to the first BLO. The first loop gain is higher than the second loop gain. A method includes receiving, in a first burst accumulator, mixed down color information directly from a first phase detector without filtering the mixed down color information, converting the composite video signal to a burst gate signal, accumulating one or more of the burst gate signal, and calculating a frequency offset for the second BLO in the first BLO expedite the calculating of the frequency offset and to compensate for the second BLO operating in the second loop gain.

Abstract: Performing a decoding mode of a frequency modulation (FM) signal for an adaptive FM radio receiver includes passing the FM signal through a FM demodulator to obtain a composite signal that includes a pilot signal and noise around the pilot signal, passing the composite signal through a band bass filter, filtering the pilot signal from the noise using a pilot and noise separator that includes a notch filter that filters the pilot signal from the noise, obtaining average amplitudes of the pilot signal and the noise, comparing a ratio between the average amplitudes of the pilot signal and the noise with a programmable threshold, and selecting a decoding mode and an audio low pass filter. The decoding mode is selected based on a quality of the pilot signal being decoded and the audio LPF is selected based on the comparison ratio.

Abstract: An apparatus and method for equalizing analog TV signals includes an antenna that receives the signal data, wherein the signal data comprises a luminance carrier comprising a luminance channel and a chrominance carrier comprising a chrominance channel; an analog-to-digital converter coupled to receiving antenna that converts the received signal data to digital signal data; an instruction memory storing digital equalizer instructions; and a digital equalizer system, coupled to the memory and the analog-to-digital converter, wherein the digital equalizer system processes the digital equalizer instructions to estimate a noise variation of the luminance channel; equalize the luminance channel; and equalize the chrominance channel, wherein the equalization of the chrominance channel is separate and distinct from the equalization of the luminance channel.

Abstract: A technique for optimizing a prediction method of samples in blocks of an image is provided. The image includes a first block, a second block, a third block, and a fourth block, each of the blocks include 8×8 blocks and form one Macro block. The method includes performing a prediction of the second block, the third block and the fourth block by performing at least one of prediction methods. A prediction error per block (Pe) is computed for each prediction method that is performed to predict the second block, the third block, and the fourth block. The prediction error per block (Pe) equals an original block value minus a predicted block value. An optimal prediction method is chosen from each of the prediction methods performed that results in minimum ?|Pe| pixels per block (summation on pixels per block). The optimal prediction method and the Pe for each block are stored.

Abstract: A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.

Abstract: A method of estimating coarse frequency offset of received symbols based on a received frequency domain sample at a kth sub-carrier of a 53rd Orthogonal Frequency Division Multiplexing (OFDM) data symbol in a jth time slot (TS) of a receiver in a China Multimedia Mobile Broadcasting (CMMB) mobile television communication network includes dividing a received sample, Ykj, into two sets of noise only tones and data plus noise tones Dkj, obtaining a received sample only if there is a coarse frequency offset mismatch between a transmitter and the receiver, dividing a summation of a power of the data plus noise tones by a summation of a power of the noise only tones to obtain ?kj, and estimating an integer coarse frequency offset estimate, ?{circumflex over (f)}Ij, of the received symbols when the ?kj is a maximum.

Abstract: Timing and frequency offset processing in sub-carriers is performed in an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) a receiver system. Sub-carriers are divided into two sub-sets, where the sub-sets contain an equal number of sub-carriers. Subsequently bad sub-carriers are removed, if present, from first sub-set of the sub-sets, and corresponding sub-carriers from a second sub-set of the sub-sets are also removed. Further, a phase difference on each sub-carrier from each sub-set is computed, and mean phase differences of each of the sub-sets are computed. Furthermore, frequency offset is computed by averaging the mean phase differences of the sets.