Patents Assigned to NEXCHIP SEMICONDUCTOR CO., LTD
  • Patent number: 11348781
    Abstract: The present disclosure provides a wafer annealing method, including: preparing a wafer, the wafer includes a plurality of regions concentrically disposed on the wafer; heating the plurality of regions, the heating process includes a plurality of heating stages, each of the heating stages has a different heating rate, temperatures of the plurality of regions vary in each of the heating stages; performing heat preservation on the plurality of regions; and cooling the plurality of regions through blowing nitrogen. The wafer annealing method can improve the electrical uniformity of the wafer.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 31, 2022
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: Yingya Shao, Houjen Chu, Binghui Bao
  • Patent number: 11257668
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate includes a first region and a second region; forming a first polycrystalline silicon layer on the substrate, wherein the first polycrystalline silicon layer covers the first region and the second region; forming a stacked structure on the first polycrystalline silicon layer; forming a protective layer on the stacked structure; forming a patterned photoresist layer on the protective layer, wherein the patterned photoresist layer exposes the protective layer in the second region; removing the protective layer and the stacked structure in the second region to expose the first polycrystalline silicon layer in the second region; removing the patterned photoresist layer; and forming a second polycrystalline silicon layer on the protective layer in the first region and the first polycrystalline silicon layer in the second region.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Nexchip Semiconductor Co., LTD
    Inventors: Yongbo Feng, Hongbo Zhu, Houyou Wang, Mingyang Tsai
  • Publication number: 20210398860
    Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
  • Publication number: 20210384083
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 9, 2021
    Applicant: Nexchip Semiconductor Co., LTD
    Inventors: Chunlong Xu, Ching-Ming Lee, Tsung-kai Yang
  • Publication number: 20210375617
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate includes a first region and a second region; forming a first polycrystalline silicon layer on the substrate, wherein the first polycrystalline silicon layer covers the first region and the second region; forming a stacked structure on the first polycrystalline silicon layer; forming a protective layer on the stacked structure; forming a patterned photoresist layer on the protective layer, wherein the patterned photoresist layer exposes the protective layer in the second region; removing the protective layer and the stacked structure in the second region to expose the first polycrystalline silicon layer in the second region; removing the patterned photoresist layer; and forming a second polycrystalline silicon layer on the protective layer in the first region and the first polycrystalline silicon layer in the second region.
    Type: Application
    Filed: July 1, 2020
    Publication date: December 2, 2021
    Applicant: Nexchip Semiconductor Co., LTD
    Inventors: Yongbo FENG, Hongbo ZHU, Houyou WANG, Mingyang TSAI
  • Publication number: 20210351029
    Abstract: The present disclosure provides a wafer annealing method, including: preparing a wafer, the wafer includes a plurality of regions concentrically disposed on the wafer; heating the plurality of regions, the heating process includes a plurality of heating stages, each of the heating stages has a different heating rate, temperatures of the plurality of regions vary in each of the heating stages; performing heat preservation on the plurality of regions; and cooling the plurality of regions through blowing nitrogen. The wafer annealing method can improve the electrical uniformity of the wafer.
    Type: Application
    Filed: July 10, 2020
    Publication date: November 11, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: YINGYA SHAO, HOUJEN CHU, BINGHUI BAO
  • Patent number: 11088155
    Abstract: The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 10, 2021
    Assignee: Nexchip Semiconductor Co., LTD
    Inventor: Geeng-Chuan Chern
  • Publication number: 20210210615
    Abstract: The present disclosure discloses a transistor structure and a method for manufacturing the same. The method includes: preparing a substrate, a plurality of gate structures are disposed on the substrate; forming a first spacer structure on both sidewalls of each gate structure; and forming a film layer, the film layer covers the substrate, the plurality of gate structures, the second spacer structure and the step structure. The present disclosure solves the problem that defects caused by growth speed differences of films at spacers of the gate structures and the substrate, such as deep pits or holes, occur in a film deposition process, thereby avoiding electricity leakage of a subsequent contact pipeline and failure of a device, thus ensuring the quality of the transistor product.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 8, 2021
    Applicant: Nexchip Semiconductor Co., LTD
    Inventors: Jing ZHANG, Qizhun JIN
  • Patent number: 11049947
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 29, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: Geeng-Chuan Chern
  • Publication number: 20210193529
    Abstract: The present disclosure provides a method for manufacturing semiconductor device and a semiconductor device formed using same. The method includes: preparing a substrate; forming a pad oxide layer and a barrier layer on the substrate, the barrier layer is disposed on the pad oxide layer; forming a plurality of shallow trench isolation structures in the substrate to form multiple regions in the substrate; removing a part of the barrier layer to form a recess, the recess is set in any one of the multiple regions, and a region directly below the recess is defined as a high voltage device region; and forming a gate oxide layer in the recess, and removing the barrier layer. The method provided in the present disclosure simplifies the manufacturing process and reduces the production costs.
    Type: Application
    Filed: April 16, 2020
    Publication date: June 24, 2021
    Applicant: Nexchip Semiconductor Co., LTD
    Inventors: Zhongxiang MA, Qingmin LI, Baihua GONG
  • Patent number: 10916664
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Grant
    Filed: September 19, 2020
    Date of Patent: February 9, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: Geeng-Chuan Chern
  • Publication number: 20210020630
    Abstract: The present disclosure provides a high-voltage tolerant semiconductor element preventing performance deterioration caused by impurity diffusion. The high-voltage tolerant semiconductor element includes a source portion (S), a well impurity region (PW) disposed around the source portion (S), and at least two gate portions (G) disposed at two sides of the source portion (S). An impurity concentration of the well impurity region is higher than an impurity concentration of a silicon substrate. A space between the two gate portions (G) is greater than a diffusion length (DD) of impurities.
    Type: Application
    Filed: June 15, 2020
    Publication date: January 21, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
  • Publication number: 20210005745
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Application
    Filed: September 19, 2020
    Publication date: January 7, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: GEENG-CHUAN CHERN
  • Patent number: 10854758
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 1, 2020
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: Geeng-Chuan Chern
  • Publication number: 20200251481
    Abstract: The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.
    Type: Application
    Filed: March 18, 2020
    Publication date: August 6, 2020
    Applicant: Nexchip Semiconductor Co., LTD
    Inventor: Geeng-Chuan Chern
  • Publication number: 20200243551
    Abstract: The present disclosure provides a non-volatile memory and a manufacturing method for the same, including: a substrate; a floating gate structure located on the substrate, the floating gate structure sequentially includes a floating gate dielectric layer and a floating gate conductive layer; a word line structure located on the floating gate structure, the word line structure sequentially includes a word line dielectric layer and a word line conductive layer; a drain region located on the substrate, the drain region is adjacent to a first edge of the floating gate structure; a source region located on the substrate, the source region is adjacent to a second edge of the floating gate structure; a peripheral doped region located on the substrate, the peripheral doped region is formed around both sides of the source region and is adjacent to the second edge of the floating gate structure.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 30, 2020
    Applicant: Nexchip Semiconductor Co., LTD.
    Inventor: Geeng-Chuan CHERN
  • Patent number: 10726894
    Abstract: The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.
    Type: Grant
    Filed: November 25, 2018
    Date of Patent: July 28, 2020
    Assignee: Nexchip Semiconductor Co., Ltd
    Inventor: Geeng-Chuan Chern
  • Publication number: 20200152649
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 14, 2020
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: GEENG-CHUAN CHERN
  • Publication number: 20200152784
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Application
    Filed: February 18, 2019
    Publication date: May 14, 2020
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: GEENG-CHUAN CHERN
  • Publication number: 20200027492
    Abstract: The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.
    Type: Application
    Filed: November 25, 2018
    Publication date: January 23, 2020
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD
    Inventor: GEENG-CHUAN CHERN