Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.
Abstract: The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.
Abstract: A split-gate non-volatile memory and a fabrication method thereof. The method comprises the following steps: 1) forming a plurality of shallow trench isolation structures in a semiconductor substrate; 2) forming word lines on the semiconductor substrate; 3) forming a source and a drain in the semiconductor substrate, and forming a floating gate on a sidewall of the word line on a side close to the source, a portion of the floating gate that contacts with the word lines presents as a sharp tip; 4) removing part of the word lines by adopting an etching process such that the sharp tip of the top portion of the floating gate is higher than the word lines; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming metal bit lines on the conductive plug.