Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Abstract: A high-dimensional data nearest-neighbor query method based on variable-length hash codes is disclosed. Specifically, in this method, hash codes with the same code frequency are taken as a sub-data set, all the sub-data sets are ranked, a compression ratio is set for each sub-data set, the sub-data sets are compressed and trained according to the compression ratios, and hash codes and original codes corresponding to the trained sub-data sets are obtained; the hash code of each trained sub-data sets is copied to obtain multiple replicas, and the original codes and the corresponding replicas are strung to obtain strung hash codes which are integrated to form a final nearest-neighbor query table; and, a query code is obtained, and the nearest-neighbor query table is searched for a nearest-neighbor data set to complete query. The query efficiency and accuracy are greatly improved according to the invention.

Abstract: The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .

Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .

Abstract: A low-profile CTS flat-plate array antenna includes a radiating layer, a mode switching layer and a feed network layer which are sequentially arrayed from top to bottom. The mode switching layer comprises a first metal plate and a mode switching cavity array arranged on an upper surface of the first metal plate and comprising 22n mode switching cavities arrayed in 2n rows and 2n columns, wherein n is an integer greater than or equal to 1. Each mode switching cavity includes a first rectangular cavity, a second rectangular cavity, a third rectangular cavity, a fourth rectangular cavity and a fifth rectangular cavity which are sequentially connected from left to right. The 2n mode switching cavities located in each row are sequentially connected end to end.

Abstract: An ultra-wideband CTS flat-plate array antenna includes a radiating layer, a mode switching layer and a feed network layer sequentially arrayed from top to bottom. The mode switching layer comprises a first metal plate and a mode switching cavity formed in the first metal plate and including two mode switching units which are arranged left and right and each includes eight H-plane Y-type single-ridge waveguide power dividers arrayed in 4 rows and 2 columns. The H-plane Y-type single-ridge waveguide power divider in the mth row and 1st column is bilaterally symmetrical with the H-plane Y-type single-ridge waveguide power divider in the mth row and 2nd column. The two H-plane Y-type single-ridge waveguide power dividers in the each row are connected through an E-plane T-type single-ridge waveguide power divider. A center distance between every two adjacent H-plane Y-type single-ridge waveguide power dividers in each column is not over one wavelength.

Abstract: A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector.

Abstract: A waveguide slotted array antenna comprises a feed layer and a radiation layer, wherein the feed layer is located below the radiation layer, and the radiation layer comprises a first radiation unit, a second radiation unit, a third radiation unit and a fourth radiation unit which are stacked from bottom to top; the first radiation unit comprises a first flat metal plate and a first radiation array arranged on the first flat metal plate, the second radiation unit comprises a second flat metal plate and a second radiation array arranged on the second flat metal plate, the third radiation unit comprises a third flat metal plate and a third radiation array arranged on the third flat metal plate, and the fourth radiation unit comprises a fourth flat metal plate and a fourth radiation array arranged on the fourth flat metal plate. The waveguide slotted array antenna has the advantages of low sidelobes and low cost while ensuring broad bands and high gains, and can be made small.

Abstract: Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.

Abstract: A static memory cell capable of balancing bit line leakage currents is characterized by including a 1st PMOS transistor, a 2nd PMOS transistor, a 1st NMOS transistor, a 2nd NMOS transistor, a 3rd NMOS transistor, a 4th NMOS transistor, a 5th NMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1st NMOS transistor, the 2nd NMOS transistor, the 3rd NMOS transistor and the 4th NMOS transistor are all normal threshold NMOS transistors. The 1st PMOS transistor and the 2nd PMOS transistor are both low threshold PMOS transistors. The 5th NMOS transistor, the 6th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Abstract: A 3D-HEVC inter-frame information hiding method based on visual perception includes steps of information embedding and information extraction. In the step of information embedding, the human visual perception characteristic is considered, stereo salient images are obtained by a stereo image salient model, and the stereo salient images are divided into salient blocks and non-salient blocks with an otsu threshold. The coding quantization parameters are modified according to different modulation rules for different regions. Then, based on the modified quantization parameters, the coding-tree-units are coded to complete the information embedding. In the step of information extraction, no original video is needed, no any side information needs to be transmitted, and the secret information can be blindly extracted.

Abstract: The present invention discloses a microscopic three-dimensional measurement system and method based on a moving diaphragm. The present invention adds the diaphragm into the existing optical microscopic imaging system to limit light irradiation angle during imaging for reducing the diameter of blur circle, which extends the depth of field and the depth measurement range, so as to achieve the three-dimensional measurement of large-size objects to be measured. Through changing the position of the added diaphragm, two images with different light incident directions are obtained, which is similar to binocular stereo vision, and then the disparity map is used to predict the depth, so as to carry out the 3D scene reconstruction. Since the depth of field of the imaging system is enlarged and the imaging model has certain non-linear characteristics, the present invention uses quadratic function to express the non-linearity, which reduces the measurement error.

Abstract: A static memory cell capable of balancing bit line leakage currents is characterized by including a 1st PMOS transistor, a 2nd PMOS transistor, a 1st NMOS transistor, a 2nd NMOS transistor, a 3rd NMOS transistor, a 4th NMOS transistor, a 5th NMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1st NMOS transistor, the 2nd NMOS transistor, the 3rd NMOS transistor and the 4th NMOS transistor are all normal threshold NMOS transistors. The 1st PMOS transistor and the 2nd PMOS transistor are both low threshold PMOS transistors. The 5th NMOS transistor, the 6th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Abstract: A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Abstract: A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector.

Abstract: A high dynamic range image information hiding method includes embedding secret information and extracting the secret information. The step of embedding secret information includes obtaining three channel values of every pixel in an original high dynamic range image; according to every channel value and corresponding 5-bit exponent of every pixel, determining an embedding significance bit of the information to be embedded in every channel value of every pixel; embedding information into every channel value of every pixel; and obtaining a high dynamic range image embedded with the secret information.