Abstract: The present invention discloses a CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, 31 CNFET tubes, 6 NTI gate circuits having the same circuit structure, 6 PTI gate circuits having the same circuit structure as well as the 1st and 2nd two-value inverters having the same circuit structure; it features in correct logic functions as well as high-speed and low power consumption.

Abstract: The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor, a 10th CNFET transistor and an 11th CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.

Abstract: The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF circuit is arranged into a 3n rows×3n columns matrix formed by 3n×3n ternary PUF units; the ternary PUF unit comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor and a 10th CNFET transistor; its advantage lies in the fact that it is provided with small circuit area and higher randomness and uniqueness while ensuring proper logic function.

Abstract: The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor, a 10th CNFET transistor and an 11th CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.

Abstract: The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF circuit is arranged into a 3n rows×3n columns matrix formed by 3n×3n ternary PUF units; the ternary PUF unit comprises a 1st CNFET transistor, a 2nd CNFET transistor, a 3rd CNFET transistor, a 4th CNFET transistor, a 5th CNFET transistor, a 6th CNFET transistor, a 7th CNFET transistor, an 8th CNFET transistor, a 9th CNFET transistor and a 10th CNFET transistor; its advantage lies in the fact that it is provided with small circuit area and higher randomness and uniqueness while ensuring proper logic function.

Abstract: A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Abstract: The present invention discloses a shift register capable of defending against DPA attack, comprising 4 master-slave D flip-flops, 12 two-input NAND/AND gates, 4 three-input NOR/OR gates and 40 inverters; the 4 master-slave D flip-flops are provided with reset function; it is based on TSMC 65 mm CMOS technique; as indicated by Spectre simulation verification, the shift register of the present invention has correct logic function with NED and NSD below 2.66% and 0.63% respectively under multi PVT combinations, which is provided with significant performance in defense differential power consumption analysis.

Abstract: A zero-watermarking registration and detection method for HEVC video streaming against requantization transcoding is provided. To increase an attack-resistance of a registration watermarking, the registration method firstly processes depth values corresponding to respective brightness blocks in a target video streaming with a depth binarization during constructing registration watermarking information through depth features, because the depth binarization well reflects a robustness of the registration watermarking. A first watermarking information matrix including a part of the depth values after the depth binarization is encrypted with a random matrix, so as to increase a safety of the registration watermarking. The registration method directly generates zero-watermarking through the depth features of the video streaming without modifying original carrier information and affecting a watermarking transparency.

Abstract: The present invention discloses a multi-port PUF circuit based on NMOS zero temperature coefficient point, comprising an input register, a deviation current source, a arbiter and a disturbing module used to construct a multi-port PUF circuit; the input register comprises m D-flip-flops; the deviation current module comprises m deviation current cells; the arbiter comprises 2n current sensitive amplifiers; the disturbing module comprises n 2-input XOR gates; wherein an input challenge used to configure deviation current generation module can update IDs without replacement of hardware. In addition, it has a capability of producing a multi-bit IDs in one clock cycle. Post-layout simulation results show that the PUF circuit is provided with excellent uniqueness and randomness with reliability up to 98.2% across temperature variation from ?40° C. to 125° C., and supply voltage variation from 1.08V to 1.32V; it can be applied in information security field.

Abstract: An objective assessment method for a stereoscopic image quality combined with manifold characteristics and binocular characteristics trains a matrix after dimensionality reduction and whitening obtained from natural scene plane images through an orthogonal locality preserving projection algorithm, for obtaining a best mapping matrix. Image blocks, not important for visual perception, are removed. After finishing selecting the image blocks, through the best mapping matrix, manifold characteristic vectors of the image blocks are extracted, and a structural distortion of a distorted image is measured according to a manifold characteristic similarity. Considering influences of an image luminance variation on human eyes, a luminance distortion of the distorted image is calculated according to a mean value of the image blocks.

Abstract: The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of

Abstract: The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 5th inverter, the 6th inverter, the 7th inverter, the 8th inverter, the 9th inverter, the 1st NAND gate, the 2nd NAND gate, the 3rd NAND gate, the 1st NOR gate, the 2nd NOR gate and the 1st PMOS tube; the 2nd NOR gate is provided with the 1st input terminal, the 2nd input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.

Abstract: The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 5th inverter, the 6th inverter, the 7th inverter, the 8th inverter, the 9th inverter, the 1st NAND gate, the 2nd NAND gate, the 3rd NAND gate, the 1st NOR gate, the 2nd NOR gate and the 1st PMOS tube; the 2nd NOR gate is provided with the 1st input terminal, the 2nd input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.

Abstract: A rapid autofocus method for a stereo microscope includes steps of: calculating a disparity of each of stereo microscopic images in a stereo microscopic calibration image sequence; extracting a clear stereo microscopic image sequence from the stereo microscopic calibration image sequence; then, finding out a largest disparity and a smallest disparity among the disparities of all the stereo microscopic images in the clear stereo microscopic image sequence; at a chosen magnification, arbitrarily acquiring a stereo microscopic image; finally, determining a disparity range according to the disparity of the acquired stereo microscopic image, the largest disparity and the smallest disparity, and realizing an autofocus of a target object in the acquired stereo microscopic images. The disparity range is obtained via once off-line calibration at the same magnification, and applicable to the autofocus at an arbitrary timing.

Abstract: An objective assessment method for a color image quality based on online manifold learning considers a relationship between a saliency and an image quality objective assessment. Through a visual saliency detection algorithm, saliency maps of a reference image and a distorted image are obtained for further obtaining a maximum fusion saliency map. Based on maximum saliencies of image blocks in the maximum fusion saliency map, a saliency difference between each reference image block and a corresponding distorted image block is measured through an absolute difference, and thus reference visual important image blocks and distorted visual important image blocks are screened and extracted. Through manifold eigenvectors of the reference visual important image blocks and the distorted visual important image blocks, an objective quality assessment value of the distorted image is calculated.

Abstract: The present invention discloses a CNFET double-edge pulse JKL flip-flop, comprising a double-edge pulse signal generator, 31 CNFET tubes, 6 NTI gate circuits having the same circuit structure, 6 PTI gate circuits having the same circuit structure as well as the 1st and 2nd two-value inverters having the same circuit structure; it features in correct logic functions as well as high-speed and low power consumption.

Abstract: A method for assessing an objective quality of a stereoscopic video based on reduced time-domain weighting, which considers a time domain perception redundant characteristic of human eyes during a video perception, includes steps of: through a motion intensity mean value and a motion intensity variance of an undistorted stereoscopic video and the motion intensity mean value and the motion intensity variance of each frame group, determining a motion intensity level of each frame group of the undistorted stereoscopic video; for the frame groups having different motion intensity levels, selecting undistorted reduced stereoscopic images through different frame extracting strategies with different densities; measuring a quality of a simultaneous distorted reduced stereoscopic image relative to the undistorted reduced stereoscopic image; through weighting each quality of the simultaneous distorted reduced stereoscopic image relative to the undistorted reduced stereoscopic image, obtaining a quality of a distorted s

Abstract: The present invention discloses a bridge imbalance PUF unit circuit and multi PUF circuits; the bridge imbalance PUF unit circuit comprises a four-arm bridge unit circuit and a contrast output unit circuit; the multi PUF circuits comprise a timing controller, a row decoder, a column decoder, a memory array, a row output circuit and a column output circuit; each memory unit in the memory array comprises a bridge imbalance PUF unit circuit and 4 NMOS tubes; the present invention features in higher randomness that is up to 51.8% at the supply voltage of 1.2V under the temperature of 25° C.

Abstract: The present invention discloses a bridge imbalance PUF unit circuit and multi PUF circuits; the bridge imbalance PUF unit circuit comprises a four-arm bridge unit circuit and a contrast output unit circuit; the multi PUF circuits comprise a timing controller, a row decoder, a column decoder, a memory array, a row output circuit and a column output circuit; each memory unit in the memory array comprises a bridge imbalance PUF unit circuit and 4 NMOS tubes; the present invention features in higher randomness that is up to 51.8% at the supply voltage of 1.2V under the temperature of 25° C.

Abstract: A video quality objective assessment method based on a spatiotemporal domain structure firstly combines a spatiotemporal domain gradient magnitude and color information for calculating a spatiotemporal domain local similarity, and then uses variance fusion for spatial domain fusion. The spatiotemporal domain local similarity is fused into frame-level objective quality value, and then a temporal domain fusion model is established by simulating three important global temporal effects, which are a smoothing effect, an asymmetric track effects and a recency effect, of a human visual system. Finally, the objective quality values of the distorted video sequence are obtained. By modeling the human visual temporal domain effect, the temporal domain weighting method of the present invention is able to accurately and efficiently evaluate the objective quality of the distorted video.