Patents Assigned to Nippon Electric Co., Ltd.
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Patent number: 4408099Abstract: A radio paging system calls a paged receiver from a first telephone, with signals sent by way of a paging terminal. Paging is carried out by the steps of (a) sending a paging signal assigned to the paging receiver and a message from the first telephone set to the paging terminal; (b) transmitting the paging signal from the paging terminal to the paging receiver via a radio frequency; (c) storing the message at the paging terminal; (d) at the paging receiver, receiving the paging signal transmitted by the step (b); (e) storing in advance the paging number for the paging receiver at the paging receiver; (f) sending tones from the paging receiver corresponding to the paging number stored by the step (e), the tones being sent to the paging terminal by way of a second telephone; and (g) sending the message stored by the step (c) to the second telephone, in response to the tones.Type: GrantFiled: June 5, 1981Date of Patent: October 4, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Daisuke Ishii
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Patent number: 4407018Abstract: A digital signal processor is disclosed suited for LSI fabrication comprising a data input circuit for carrying out scaling on a plurality of serial data supplied through a first external terminal group; a coefficient input circuit for carrying out 2's complement conversion on a plurality of specific data from a plurality of serial data supplied through a second external terminal group; a multiplier circuit for carrying out a plurality of multiplications and additions on data from the data input and coefficient input circuits; and an adder circuit for carrying out a plurality of additions and subtractions as well as overflow detection and correction. Data connections in each of the circuits are altered depending on a combination of logical zeros and ones entered through a fourth external terminal group so that one of a plurality of functional modes is selected.Type: GrantFiled: April 10, 1981Date of Patent: September 27, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Akira Kanemasa
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Patent number: 4404672Abstract: In a digital subscriber set (31) in which a line receiver (36) receives, when enabled, digital signal bursts from a master terminal (32) and in which a line driver (37) sends, when enabled, digital signal bursts to the master terminal in synchronism with the signal bursts received from the master terminal, a circuit (67, 69, 71, 72) temporarily disables and enables the line receiver and the line driver to send a call orignating signal to the master terminal and then enables and disables the line receiver and the line driver continuously until synchronism is established by at least one digital signal burst which the master terminal supplies to the subscriber set in response to the call originating signal. The circuit recovers synchronism within the shortest possible time when synchronism is lost for any reason during communication.Type: GrantFiled: March 19, 1981Date of Patent: September 13, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Hiroshi Shimizu
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Patent number: 4403223Abstract: A demand ink-jet printer uses droplets of conductive ink for recording on a recording medium. In greater detail, an ink chamber, filled with conductive ink, has a nozzle in one wall and a piezoelectric member attached to another wall. Droplets of ink are driven out the nozzle in response to a driving pulse applied to the piezoelectric member. The energy content of the driving pulses controls both the size of the droplets and the potential of a charging voltage applied to the droplets. This way, the combined charge and size may be held constant so that large or small drops may be generated to produce half-tone pictures and the droplets may be electrostatically deflected accurately, despite the variance in droplet size.Type: GrantFiled: February 17, 1981Date of Patent: September 6, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Mitsuo Tsuzuki, Michihisa Suga
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Patent number: 4403114Abstract: Speaker recognition is decided by a similarity measure (D) calculated from comparing selected feature vectors among an input speech signal sequence of feature vectors (A) and a selected sequence (B) of reference vectors selected from a plurality of pre-stored reference sequences. Prior to comparison of the input and reference vector sequences, the two sequences are time normalized to align corresponding feature vectors. A significant sound specifying signal (V) including a time sequence of elementary signals is generated in synchronism with one of the input and reference sequences and indicates which feature vectors in that one of the input and reference sequences are considered to represent significant sound. The similarity measure (D) is then calculated in accordance with the comparison of those feature vectors in the one sequence which are indicated by the significant sound specifying signal as representing significant sound and the corresponding feature vectors of the other sequence.Type: GrantFiled: June 30, 1981Date of Patent: September 6, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Hiroaki Sakoe
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Patent number: 4403212Abstract: A paging communication receiver receives carrier waves modulated by a sequence of signals comprising a calling signal, a display information signal and a discriminating signal. The modulated carrier wave is demodulated to retrieve the calling signal, display information signal and discriminating signal. The calling signal is detected and decoded to provide a detection signal, when the discriminating signal represents a calling signal. The detection signal causes a decoding for displaying information when the discriminating signal is the one representing the display information signal.Type: GrantFiled: October 6, 1980Date of Patent: September 6, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Masaru Masaki
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Patent number: 4401982Abstract: In a fluorescent display tube provided with a plurality of electrically isolated grids, spacings for electrically isolating the grids are arranged to divide portions of an anode to be integrally displayed.Type: GrantFiled: May 1, 1981Date of Patent: August 30, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Togo Miyazaki, Junichi Suehiro
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Patent number: 4400782Abstract: In a monitoring system for protecting a metal pipe against corrosion, transmission of monitoring signals is carried out by the use of the pipe itself as a transmission line between a center station and a substation, which are coupled to the pipe at center and subordinate locations, respectively. The substation sends data signals over the pipe to the center station. These data signals represent the degree of corrosion that is measured at the subordinate location and are monitored by the center station. When a plurality of substations are coupled to the pipe, the center station selects a substation by transmitting through the pipe an address assigned to the substation. Each substation returns the assigned address to the center station in combination with the signals representing the measured degree of corrosion at the addressed substation. Preferably, the center station produces the selected address twice while each substation produces the assigned address and the measured corrosion signal, twice.Type: GrantFiled: February 25, 1981Date of Patent: August 23, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Masashi Ishikawa, Masatoshi Shimada, Katsutomo Okamoto, Shigeyoshi Sugita, Masayuki Goto, Yukuo Koizumi, Osamu Kaneda
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Patent number: 4399521Abstract: In a semiconductor memory device of the type having PNPN elements for transferring checking and programming currents to a memory cell, and a trigger circuit for activating the PNPN elements at a predetermined potential, a voltage limiting circuit is provided to activate the PNPN elements prior to achieving the triggering potential so that large voltage spikes through the memory elements during the memory checking operation can be prevented.Type: GrantFiled: September 26, 1980Date of Patent: August 16, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Hajime Masuda
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Patent number: 4398266Abstract: An integrated circuit provided with at least one field-programmable element matrix which is reduced in size and improved in an electrical characteristics is disclosed. The circuit is characterized in that the matrix is physically divided into at least two separate parts, at least a part of a logic circuit for applying a logic input to the matrix or for receiving a logic output from the matrix in a read mode is disposed outside of the separate parts of the matrix, and at least a part of a selection circuit for writing or programming the matrix is disposed between the two divided parts of the matrix.Type: GrantFiled: July 29, 1980Date of Patent: August 9, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Teiji Tamura, Hiroshi Mayumi
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Patent number: 4398208Abstract: An integrated circuit (IC) chip package comprises a plurality of IC chips mounted on a multilayer substrate. A plurality of covers are provided on the substrate and are positioned so as to cover at least one of the IC chips. External pins are provided on each of the covers, and each of the pins is connected to selected chips via first signal lines on the covers connecting the pins to the substrate, and second signal lines within the substrate connecting the first signal lines to the selected chips. The substrate may be provided with a heat exchanger or heat sinks at the underside thereof, the overall construction resulting in a cool operating IC chip package with numerous external terminals having short wiring lengths to the chips.Type: GrantFiled: July 10, 1980Date of Patent: August 9, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Hiroshi Murano, Moritoshi Akino
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Patent number: 4398291Abstract: On carrying out communication among a plurality of earth stations by the use of a satellite, super-frame time slots are specified on board the satellite at a super-frame period equal to a frame period multiplied by a predetermined natural number in order to synchronize the satellite and the earth stations with the super-frame time slots. The satellite informs each earth station of the super-frame time slots by generating super-frame bursts specifying the super-frame time slots. Alternatively, each earth station generates super-frame bursts to enter the super-frame time slots on the satellite. The satellite informs such earth station of the super-frame time slots by preventing the super-frame bursts from being returned to each station. At any rate, the satellite and each station change one on-line sequence of operation to the other in synchronism with a specified one of the super-frame time slots without any interruption of communication.Type: GrantFiled: June 22, 1981Date of Patent: August 9, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Toshinori Hotta, Yukio Takimoto
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Patent number: 4397017Abstract: It has now been confirmed as regards a stuff (justification) synchronization device for each of plesiochronous input pulse sequence to be time division multiplexed that a low frequency jitter component appears in a synchronous output pulse sequence from the effect of sampling phase lags of read pulse sequences for reading the output pulse sequence for stuffing from an elastic memory (36) of the device relative to write pulse sequences for storing the input pulse sequence in the memory at a sampling interval equal to the memory capacity. The jitter is reduced (1) by selecting a prime number, preferably thirteen and more preferably seventeen or nineteen, as the memory capacity, (2) by cyclically using selected write and read pulse sequences for phase lag monitoring, or (3) by rendering the sampling interval either random or equivalently random.Type: GrantFiled: March 2, 1981Date of Patent: August 2, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Yoshinori Rokugo
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Patent number: 4396951Abstract: A solid-state imaging apparatus has an optical iris and a CCD imaging device which responds to light received from an object for producing a picture signal component and a reference black level signal component. A limiter limits the amplitude of the black level component to less than a predetermined value and the amplitude of the reference black level signal component is higher when the CCD imaging device is receiving such a quantity of light that the electric charges generated by photo-charge conversion in the light-sensitive elements in the CCD imaging device may not overflow from the light-sensitive elements. The limited amplitude is lower than the amplitude of the reference black signal component when the electric charges generated by photo-charge conversion in the light-sensitive elements overflow from the light-sensitive elements.Type: GrantFiled: June 23, 1981Date of Patent: August 2, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Takanori Tanaka
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Patent number: 4396939Abstract: A chromakey effect apparatus including a color-killing subcarrier-generating circuit which generates a color-killing subcarrier which completely kills color even when the hue or saturation of the chromakey area is changed and which also kills the color while simultaneously converting the color. Furthermore, the apparatus is capable of both chromakeying only the chromakey area even when there are many portions having the same color as the chromakey area, and also chromakeying a desired portion even when the desired portion includes a part having different colors. In addition, the apparatus is capable of inserting another television signal into only a desired portion of the chromakey area and of converting the color of the remaining portion of the chromakey area.Type: GrantFiled: June 4, 1981Date of Patent: August 2, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Isamu Kitahama
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Patent number: 4397000Abstract: An output buffer circuit operable at a high-speed and stably holding output level is disclosed. The output buffer circuit comprises a pair of input transistors receivivable a true and a complementary signals, a pair of output nodes from which amplified signals of the true and complementary signals are derived, a pair of switching gates coupled between the drains of the input transistors and the output nodes and control means for operatively disenabling the switching gates when logic state of the true and complementary signals applied to the input transistors is reversed.Type: GrantFiled: January 19, 1981Date of Patent: August 2, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Akira Nagami
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Patent number: 4395595Abstract: A digital pushbutton (PB) signalling receiver having reduced sampling frequency for reducing the operations required by digital filters. The PB receiver is responsive to an in-band audio signal digitized at a conventional sampling frequency (e.g., 8 KHz) and detects two PB frequencies, one from a lower group and one from a higher group of frequencies. The input signal is successively digitally filtered and sampled, with each sampling frequency being reduced by 1/2 from the preceeding sampling frequency. This results in two digitized outputs, both of which are much lower sampled digitized signals than the input, and each of which contains information corresponding to said lower and higher groups of frequencies, respectively. The two outputs are then applied to two banks of frequency detectors, comprising digital band-pass filters and energy calculating circuits, for providing an indication of the presence of the lower and higher group of frequencies in the original input signal.Type: GrantFiled: April 7, 1981Date of Patent: July 26, 1983Assignee: Nippon Electric Co., Ltd.Inventors: Takao Nishitani, Tadaharu Kato
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Patent number: 4395644Abstract: A boot strap type circuit which can raise an output potential up to a power supply voltage irrespective of a condition of an input signal is disclosed. The circuit is characterized by comprising a series circuit coupled between a first end of a capacitor, from which end a boot strapped voltage is derived, and a reference voltage, the series circuit being responsive to transition of the input signal for pulling down a potential at the first end of the capacitor after a predetermined delay from that transition.Type: GrantFiled: August 13, 1980Date of Patent: July 26, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Tetsuo Misaizu
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Patent number: 4395764Abstract: A memory device which is effectively utilized as serial access memory with variable shift length of stored data is disclosed. The memory device comprises memory cells arrayed in a matrix form, a shift register whose output is used for selecting memory cells and control means for varying shift length of the shift register.Type: GrantFiled: December 29, 1980Date of Patent: July 26, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Shigeki Matsue
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Patent number: 4394713Abstract: A package construction has electrodes of a double layer capacitor element located on the opposite sides of the element. All of the electrodes are led out in the same direction. A pair of electrode plates are disposed on the element with an insulator plate having a through-hole interposed between the two plates. A terminal of an inner electrode plate penetrates through the through-hole in the insulator plate and through an aperture formed in the outer electrode plate. The capacitor is assembled in such manner that the inner electrode plate is electrically connected to one electrode of the element, while the outer electrode plate is electrically connected to the other electrode of the element via a conductive casing.Type: GrantFiled: December 5, 1980Date of Patent: July 19, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Kazunori Yoshida