Patents Assigned to Nippon Electric Co., Ltd.
  • Patent number: 4459676
    Abstract: A picture image producing apparatus has a control unit for designating picture image calculation, a display unit for displaying a picture image, and a processing unit for storing standard information used in the picture image calculation. The standard information is x-coordinate data and y-coordinate data of the picture image to be displayed. A first calculator computes a first group information of the picture image, in response to vary the x-coordinate data of the standard information. A second calculation computes second group information of the picture image in response to the varying y-coordinate data of the standard information. The picture image information of the first and second group information is transferred to the display unit.
    Type: Grant
    Filed: June 18, 1981
    Date of Patent: July 10, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Tetsuji Oguchi
  • Patent number: 4459681
    Abstract: A first-in-first-out memory device which is operable at a high-speed is disclosed. The memory device comprises a plural stages of memory units and a plural stages of control unit, each of the control units including a circuit for indicating whether its stage holds effective data or not, a circuit for receiving a signal of the indicating means of the previous stage, and a circuit generating a write signal when the memory cell holds no effective data and the previous stage hold effective data, in which the write signal is used to remove data stored in the previous memory cell to the corresponding stage memory cell.
    Type: Grant
    Filed: April 2, 1982
    Date of Patent: July 10, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Toshinori Ohtsuka
  • Patent number: 4458286
    Abstract: An electronic device for use in an automobile includes first and second power transistors connected in series between two power supply terminals, a first detector producing a first detection signal when the voltage difference between the two power supply terminals is larger than a first predetermined value, and a second detector producing a second detection signal when the voltage difference between the two power supply terminals is larger than a second predetermined value which is larger than the first value, the first power transistor being driven into cut-off in response to the first detection signal and a control current to be applied to the second power transistor being bypassed to one of the power supply terminals to keep the second power transistor conductive.
    Type: Grant
    Filed: August 30, 1982
    Date of Patent: July 3, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Eiichi Matsumura
  • Patent number: 4457286
    Abstract: An engine ignition system connected between an engine crank and ignition coils includes a reference position signal generating device having reference position sensors, and a crank angle sensing device. The ignition system also includes a signal processing device which receives both the reference position signals and crank angle signals, and when one of the reference position signals is absent continues to generate ignition control signals which activate the ignition coils. The signal processing device includes a counter which counts the crank angle signals and which is reset by the reference position signals, and a decoder which produces a signal when a count value reaches a predetermined count. The signal processing device also includes a logic circuit and a flip-flop for producing either primary ignition control signals or replacement ignition control signals. The replacement ignition control signals are generated when one of the reference position signals is absent.
    Type: Grant
    Filed: June 29, 1982
    Date of Patent: July 3, 1984
    Assignees: New Nippon Electric Co., Ltd., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroomi Katayama, Masahiko Fujii, Yoshiaki Hirosawa
  • Patent number: 4456893
    Abstract: An equalizer of a transversal filter type is given a substantially constant gain at a preselected frequency (f.sub.p) in a predetermined frequency band of an input and an output signal. For this purpose, the output signal is given by multiplying the routine transversal filter output by a reciprocal of an absolute value of a sum of complex tap gains (C.sub.1 to C.sub.N+1). Alternatively, the input signal and successively delayed signals (IN and D.sub.1 to D.sub.N) may be multiplied by the reciprocal before summation. It is possible to approximate the reciprocal by omitting those of the tap gains which are near both ends (as C.sub.1 and C.sub.N+1).
    Type: Grant
    Filed: August 16, 1982
    Date of Patent: June 26, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Susumu Otani
  • Patent number: 4457018
    Abstract: A vehicle radio telephone system is constructed to talk between a vehicle and a fixed station through any one of a plurality of radio channels. Upon degradation of a talking condition during talking, the radio channel is switched and a tone is sent to talkers to inform them that the radio channel is now being changed.
    Type: Grant
    Filed: May 3, 1983
    Date of Patent: June 26, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yoshikazu Takayama
  • Patent number: 4456850
    Abstract: A piezoelectric composite thin-film resonator has good temperature stability and resonance response, in a fundamental thickness-extensional vibration mode. Spurious vibrations caused by even-number order harmonic overtones are suppressed. The resonator has a thin film of SiO.sub.2 or other materials having a resonant frequency temperature coefficient which is opposite to that of the piezoelectric material. The SiO.sub.2 layer is inserted between two thin films of ZnO, CdS, AlN, or other piezoelectric materials. This sandwiched structure is positioned between a pair of electrode films and is supported by an insulative or a semiconductive film which is in turn fixed to a substrate. The thicknesses of the thin films have values such that an overall temperature coefficient of the resonant frequency may be at or near substantially zero. In order to better remove the even-number order harmonics, it is preferable to cover the upper electrode film with a thin film of semiconductor or insulator material.
    Type: Grant
    Filed: February 9, 1983
    Date of Patent: June 26, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Takeshi Inoue, Yoichi Miyasaka
  • Patent number: 4456952
    Abstract: A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store.
    Type: Grant
    Filed: November 6, 1980
    Date of Patent: June 26, 1984
    Assignees: Honeywell Information Systems Inc., Nippon Electric Co., Ltd., Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Edward A. Mohrman, Tsunetaka Umeno, Fumitaka Sato
  • Patent number: 4456318
    Abstract: An IC socket for a flat IC package comprises a socket substrate, a cover member, a rotary lever, and a locking/unlocking mechanism so as to obtain stable, reliable contact and stable, easy release of contact between the conductors of the flat IC package and the contact pieces of the IC socket. The locking/unlocking mechanism makes use of sliding movement of the cover member on the socket substrate on the basis of the rotation of the rotary lever.
    Type: Grant
    Filed: August 11, 1982
    Date of Patent: June 26, 1984
    Assignees: Yamaichi Electric Mfg. Co., Ltd., Nippon Electric Co., Ltd.
    Inventors: Sueji Shibata, Shoji Umesato
  • Patent number: 4456977
    Abstract: A semiconductor memory device having a large memory capacity and an improved read-out function is disclosed. The device comprises a plurality of word lines extended in the row direction, a plurality of pairs of data lines extended in the column direction and arranged in parallel, a plurality of memory cells arranged at the cross-points between the word lines and the data lines, and a plurality of sense amplifiers each coupled to each pair of the data lines, and is featured in that n (an integer of two or more) sense amplifiers are arrayed respectively in the column direction and are arranged for every n pairs of data lines in the row direction.
    Type: Grant
    Filed: March 13, 1981
    Date of Patent: June 26, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Mineo Hayashi
  • Patent number: 4455609
    Abstract: Apparatus for realtime fast reconstruction and display of dose distribution which calculates the dose of absorbed radiation in an irradiated area defined by coordinates and displays the results of the calculation. The apparatus comprises an input unit capable of setting parameters in the form of time-continuous quantities; a dedicated digital computer serving to control the input by the input unit; and a dedicated fast reconstructer for calculating the absorbed dose for each coordinate in the exposed area at a high speed by decomposing calculation formulae necessary for obtaining isodose curves on the basis of the parameter set in the input unit and effecting parallel calculation of the decomposed formulae, thereby obtaining the isodose curves; and video display for storing and displaying the isodose curves classified in terms of different isodose levels. The calculation is normally cyclically repeated to provide a motion picture of the dose distribution when the magnitude of the parameters is varied.
    Type: Grant
    Filed: September 10, 1981
    Date of Patent: June 19, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kiyonari Inamura, Yasuo Ueda, Nobumasa Furushima, Keisuke Shigaki
  • Patent number: 4455676
    Abstract: A speech processor having microprocessor control of the amplitude level of input speech signals. Input speech signals are applied to a digitally controlled level regulator, the output of which is converted into a digital speech signal for further speech processing. The peak level of the digital speech signals over a frame period is compared in the microprocessor with a preset optimum range. If the peak level falls outside the optimum range, control signals for the level regulator are adjusted in a direction to change the amplification/attenuation amount of the level regulator to bring the peak level within the optimum range.
    Type: Grant
    Filed: March 4, 1982
    Date of Patent: June 19, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroyuki Kaneda
  • Patent number: 4455556
    Abstract: In a distance measuring equipment for measuring the distance between an interrogator and a transponder with high precision by detecting the time from transmission of an interrogation pulse from the interrogator to reception of a reply pulse transmitted from the transponder on the basis of timing positions of said respective pulses; as leading edges of the interrogation pulse and reply pulse, a waveform represented by the formula of: ##EQU1## where E and F represent finite positive values and T represents time, is used, or else as a leading edge of the interrogation pulse, a waveform which can be approximated by the above formula is used, while as a leading edge of the reply pulse, a waveform obtained by passing a waveform approximately expressed by the formula of: ##EQU2## through a low-pass filter having a predetermined cut-off frequency, is used.
    Type: Grant
    Filed: May 12, 1981
    Date of Patent: June 19, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Tatsukichi Koshio, Osamu Okamoto
  • Patent number: 4453256
    Abstract: An adaptive equalizer system for quadrature amplitude modulated waves is disclosed herein. The equalizer system comprises a circuit for equalizing the received signal as a function of a composite control signal; a circuit for generating a first control signal as a function of the deviation of the equalized signal from a zero-forced waveform; a circuit for generating a second control signal as a function of the asynchronization of the equalizer system; and an output circuit for processing both of said first control signal and said second control signal, producing the composite control signal which controls the equalizing means of the equalizer system.
    Type: Grant
    Filed: December 22, 1981
    Date of Patent: June 5, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Toshihiko Ryu
  • Patent number: 4453230
    Abstract: An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between virtual and real addresses stored in a main memory. The associative memory includes first and second memories for storing a part of the correspondence between virtual and real addresses. The second memory is essentially a set associative memory but is not connected with address comparators directly. The first memory is higher in speed but smaller in capacity than the second memory. When the first memory stores the correspondence between the virtual and real address corresponding to the applied virtual address, the real address corresponding to the applied virtual address is immediately delivered.
    Type: Grant
    Filed: June 21, 1982
    Date of Patent: June 5, 1984
    Assignees: Tokyo Shibaura Electric Co., Ltd., Nippon Electric Co., Ltd.
    Inventors: Tetsuya Mizoguchi, Fumitaka Sato, Tadanobu Furukatsu
  • Patent number: 4451906
    Abstract: An improved memory device operable at a high-speed is disclosed. The memory device comprises a pair of bit lines, a sense amplifier having a pair of input terminals, a pair of control gates coupled between the pair of bit lines and the pair of input terminals of the sense amplifier, a pair of bus lines, and a pair of transfer gates connecting the input nodes of the sense amplifier to the pair of bus lines without via the control gates.
    Type: Grant
    Filed: September 17, 1981
    Date of Patent: May 29, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroaki Ikeda
  • Patent number: 4450474
    Abstract: Synchronizing signals in a PAL system are generated without the need for an n f.sub.H oscillator by generating a reference signal having 568 cycles per line, adding a half cycle per line and then substracting one cycle per field. Pre-synchronizing signals are generated from the processed reference signal and the pre-synchronizing signals are then phase shifted by an amount which varies linearly with respect to elapsed time during each field from a value of zero to a value of substantially 1/(2 f.sub.sc).
    Type: Grant
    Filed: April 5, 1982
    Date of Patent: May 22, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Mineo Mizukami
  • Patent number: 4450470
    Abstract: An integrated circuit device of large scale integration and a method of manufacturing the same makes possible high density packing of circuit elements by eliminating a great number of very minute contact holes. Instead, a circuit-element connector comprised of a polycrystalline silicon wiring path is formed by selective oxidation. Impurity atoms are introduced into the semiconductor substrate through the polycrystalline silicon circuit-element connector to form a desired circuit element. A layer of high-conductive material is provided on the polycrystalline silicon layer.
    Type: Grant
    Filed: February 12, 1979
    Date of Patent: May 22, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4450240
    Abstract: The ceramic composition comprises lead magnesium tungstate [Pb(Mg1/2 W1/2)O.sub.3 ], lead titanate [PbTiO.sub.3 ] and lead nickel niobate [Pb(Ni1/3 Nb2/3)O.sub.3 ]. When the ternary composition is expressed by [Pb(Mg1/2 W1/2)O.sub.3 ]x [PbTiO.sub.3 ]y [Pb(Ni1/3Nb2/3)O.sub.3 ]z where x+y+z=1.00, it lies on lines interconnecting five points (x=0.693, y=0.297, z=0.01), (x=0.495, y=0.495, z=0.01), (x=0.195, y=0.465, z=0.35), (x=0.10, y=0.40, z=0.50) and (x=0.06, y=0.24, z=0.70) and in a region bonded by the lines. In modifications, for the purpose of improving the mechanical strength, 0.02 to 3 mol % of at least one auxiliary ingredient selected from the group consisting of Nb, Ta and Sb, 0.05 to 8 mol % of [Pb(Mn1/3 Ta2/3)O.sub.3 ] 0.05 to 10 mol % of [Pb(Mn1/3 Nb2/3)O.sub.3 ] or 0.05 to 6 mol % of [Pb(Mn1/3 Sb2/3)O.sub.3 ] is added.
    Type: Grant
    Filed: March 15, 1983
    Date of Patent: May 22, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Haruhiko Miyamoto, Masatomo Yonezawa
  • Patent number: 4446789
    Abstract: A dot matrix printer having a printer hammer bank carried on a frame to allow movement parallel to the platen. A balancing member is suspended from the head hammer bank by resilient springs and carries a motor for driving the head hammer bank in a reciprocating manner. A linkage further couples the head hammer bank and the balancing member so that the balancing member moves in a direction opposite to that of the head hammer bank.
    Type: Grant
    Filed: December 1, 1981
    Date of Patent: May 8, 1984
    Assignees: Nippon Electric Co., Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Michio Matsumoto, Masao Kitamura, Masataka Ohta, Takeshi Ohshima