Patents Assigned to Nippon Electric Company Limited
  • Patent number: 3942066
    Abstract: In a velocity modulation tube comprising a floating prebuncher and at least one final prebuncher, frequencies of respective fundamental modes of resonance of the input cavity, the floating prebuncher, and the final buncher are adjusted to the lowest frequency of the passband of the tube, adjacent to the highest frequency of the passband, and higher than the highest frequency, respectively. Furthermore, the Q-value of the floating prebuncher is made equal to or lower than that of the input cavity. Naturally, the output cavity has its fundamental mode of resonance approximately at the center of the passband.
    Type: Grant
    Filed: February 24, 1975
    Date of Patent: March 2, 1976
    Assignee: Nippon Electric Company Limited
    Inventors: Takao Kageyama, Yosihiro Morizumi
  • Patent number: 3942118
    Abstract: A delay circuit provides a flat delay versus frequency characteristic over a first band of frequencies by combining two delay equalizers having opposite signed and equal magnitude slopes of delay versus frequency over two different bands of frequencies. The first frequency band is translated to a second band which is applied to the first of two delay equalizers. The latter has a transfer characteristic which is a substantially constant slope of delay versus frequency for a band encompassing and much wider than said second band. The output of the latter element is translated back to the first frequency band. The first band, either prior to the initial frequency translation or subsequent to the second frequency translation, is applied to a second delay equalizer. The characteristic slopes of the two delay equalizers are of substantially equal magnitude but of opposite sign.
    Type: Grant
    Filed: September 30, 1974
    Date of Patent: March 2, 1976
    Assignee: Nippon Electric Company Limited
    Inventor: Haruo Shiki
  • Patent number: 3937906
    Abstract: A telephone hook switch is manufactured by first molding a moldable insulating material into two block portions and an integral bridge. The block portions have a common back surface, adjacent parallel side surfaces having opposed and aligned back edges interconnected by the bridge, a pair of pivot members aligned on a plane perpendicular to the side surfaces and equally spaced therefrom, and slots formed in the respective block portions parallel to the side surfaces and spaced from the pivot members. The bridge has a thin portion bisecting the distance between the side surfaces. Contact members of the switch are snugly placed in predetermined ones of the slots and one of the block portions is folded at the thin portion of the bridge towards the other with the back surfaces of the respective block portions brought into substantial contact with each other. A lever member of the switch is mounted on the pivot members.
    Type: Grant
    Filed: January 31, 1974
    Date of Patent: February 10, 1976
    Assignee: Nippon Electric Company, Limited
    Inventor: Keizou Ohta
  • Patent number: 3936857
    Abstract: An insulated gate field effect transistor having improved high-frequency operating characteristics includes an extended region electrically connected to one of the source and drain regions and spaced from the surface of the substrate. The extended region extends toward the other of the source and drain regions such that the distance between the source and drain regions is relatively small within the substrate and relatively large at the surface of the substrate.
    Type: Grant
    Filed: June 28, 1974
    Date of Patent: February 3, 1976
    Assignee: Nippon Electric Company Limited
    Inventor: Michihiro Ota
  • Patent number: 3936321
    Abstract: A method is provided for making a semiconductor layer having a high resistivity comprising the steps of implanting ions into a semiconductor comprising gallium and arsenic at a first acceleration voltage at a concentration higher than the limit of solid solubility of said ions in said semiconductor, the ions being of a material which forms a deep energy level in said semiconductor; implanting protons into said semiconductor at an acceleration voltage less than said first acceleration voltage; and then heating the semiconductor, for example, from 300.degree.C to 700.degree.C.
    Type: Grant
    Filed: January 25, 1974
    Date of Patent: February 3, 1976
    Assignee: Nippon Electric Company Limited
    Inventor: Daizaburo Shinoda
  • Patent number: 3934717
    Abstract: Apparatus for orienting flat articles having straight edges such that a long edge of the article is brought into or retained in contact with the bottom surface of a transport path. The apparatus comprises an upwardly open, U-shaped transport path and at least one member disposed above the U-shaped transport path by a predetermined distance and having a surface in a plane generally perpendicular to the bottom of the U-shaped transport path and oriented at an acute angle to the flow of flat articles in the U-shaped transport path. In the preferred embodiment, the bottom of the U-shaped transport path is an upwardly inclined conveyor, and a plurality of the members are positioned along the U-shaped transport path at angles which alternate in sense.
    Type: Grant
    Filed: March 25, 1974
    Date of Patent: January 27, 1976
    Assignee: Nippon Electric Company Limited
    Inventors: Takeo Katagiri, Shinichi Fujiwara
  • Patent number: 3931007
    Abstract: A method is provided for extracting metal impurities from waste water to which ferrous ions are added to provide at least two times the amount of ferrous ions on the mol basis to the amount of metal ions present, the resulting solution containing acid radicals, a base being added to the solution to raise the pH to form a suspension of metal hydroxides, following which an oxidizing gas is bubbled in solution to form crystals containing ferric ions and further containing the metal ions originally in solution, the precipitated crystals being thereafter separated to provide clean water.
    Type: Grant
    Filed: December 17, 1973
    Date of Patent: January 6, 1976
    Assignee: Nippon Electric Company Limited
    Inventors: Izuru Sugano, Toshiro Tsuji, Masaru Kanamori
  • Patent number: 3931537
    Abstract: A gas discharge display panel having row and column electrodes for displaying a plurality of patterns arranged in rows and columns comprises a pair of dielectric plates on which the row and column electrodes are respectively formed. The column electrodes are divided into groups assigned to the patterns in the respective columns. Terminal areas connected to the column electrodes of every other groups are disposed along different edge portions of the plate disposed parallel to the rows, whereby the terminal areas are spaced wider than the electrodes.
    Type: Grant
    Filed: February 4, 1974
    Date of Patent: January 6, 1976
    Assignee: Nippon Electric Company Limited
    Inventors: Kazunori Nishida, Isao Inomata