Abstract: A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Abstract: A semiconductor component includes, before molding, a lead frame, a semiconductor chip mounted on the lead frame, and bonding wires for connecting pads of the semiconductor chip to inner leads. This component is inserted between a lower mold and an upper mold having a mold cavity moving unit, and these molds are clamped. Thereafter, an inner space formed by these clamped molds is filled with resin to form a package. Particularly, before resin filling, the mold cavity moving unit is moved downward and presses upper portions of the bonding wires to regulate the wire height. In this state, the inner space of these molds is filled with the resin. Before the filling resin is cured, the mold cavity moving unit is returned to the upper surface position of the package to form a nonfilling space in these molds. Thereafter, the nonfilling space is filled with the resin.

Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A semiconductor device of this invention has an LOC (Lead On Chip) structure, and a protective film consisting of a thermoplastic (thermosetting) resin material such as a thermoplastic (thermosetting) polyimide resin or a thermoplastic (thermosetting) polyamide resin is formed on the surface of a semiconductor chip having a DRAM. The lower surface of a lead frame is positioned to the upper surface of the semiconductor chip, on which the protective film is formed, and the upper surface of the semiconductor chip is bonded and fixed to the lower surface of the distal end portion of an inner lead with only the protective film interposed therebetween such that bonding pads appear between opposing bus bars. According to this invention, the protective film serves not only as an &agr;-ray protective film but also as an insulating material and an adhesive material.

Abstract: The present invention is to provide a method of remodeling an existing clean room building into a clean room which satisfies a new required specification. A working room (11) is expanded by removing a wall (29) between the working room (11) and a general passage (30). If a portion of the floor of the working room (11) is not the grated panel structure, such floor portion is formed as the grated panel structure by remodeling and the floor is formed as a perforated free access floor. The whole of the ceiling of the working room (11) is formed as a system ceiling of a frame structure from which a dust-collecting filter whose unit size is 600×1200 mm can be made freely detachable if necessary, and a ULPA filter is disposed on a portion which is requested to have a high cleanliness. An air-insulating panel of the same size may be attached to a portion which does not require the dust-collecting filter. An existing air conditioner that has been in use before remodeling is used as the air conditioner as it is.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A semiconductor integrated circuit has P-channel active MOSFETs and N-channel active MOSFETs formed in a semiconductor substrate. In order to electrically isolate the active MOSFETs, the semiconductor integrated circuit has P-channel field shield MOS devices and N-channel field shield MOS devices. The P-channel field shield MOS devices have field shield electrodes which are laid on regions between impurity diffusion regions of the P-channel active MOSFETs. The N-channel field shield MOS devices have field shield electrodes which are laid on regions between impurity diffusion regions of N-channel active MOSFETs. A P-channel field shield voltage, which is higher than a power supply voltage of the semiconductor integrated circuit, is supplied to the field shield electrodes of the P-channel field shield MOS device to turn the P-channel field shield MOS devices to an OFF-state to electrically isolate the P-channel active MOSFETs.

Abstract: The invention involves technology related to chemical mechanical polishing using a chemical mechanical polishing apparatus having a wafer carrier for holding a semiconductor wafer, a polishing platen which is able to be rotated and which is positioned facing the surface of the wafer carrier on which the wafer is held, and a circular polishing cloth mounted on the polishing platen for polishing the semiconductor wafer, the polishing cloth having a smaller diameter than the diameter of the semiconductor wafer, and the polishing platen being movable horizontally across the surface of the semiconductor wafer. While rotating the semiconductor wafer held on the wafer carrier, the polishing platen is moved horizontally across the surface of the semiconductor wafer so that the displacement velocity of the polishing platen is slower at a central portion of the semiconductor wafer than at an outer portion, and the surface of the semiconductor wafer is polished with the polishing cloth.

Abstract: A semiconductor device of this invention includes a semiconductor chip on which a device is formed, inner leads reaching the periphery of the semiconductor chip, and bonding wires for electrically connecting the semiconductor chip and the inner leads. The semiconductor chip is fixed on a die pad portion, and a chip fixing inner lead is integrated with the die pad portion. To simplify the bonding wire connection process and improve the reliability, the chip fixing inner lead has a step portion so that the die pad portion is formed at a lower position than the inner leads. The step portion is formed so as to be offset from a line of the end portions of the inner leads in the opposite direction of the semiconductor chip, so an arbitrary bonding wire can be kept apart from the step portion.

Abstract: In a method of manufacturing a resin-encapsulated semiconductor package, a protective film is formed on the surface of a semiconductor chip on which chip electrodes are formed, and openings are formed in the protective film to expose at least part of each chip electrode. Subsequently, conductive balls serving as external connecting terminals are fitted in these openings and connected to the chip electrodes, and all surfaces of the semiconductor chip and the conductive balls are encapsulated with a resin. Finally, the surface of the resin formed on the conductive balls is polished to partially expose the conductive balls. Since a mold need not have pins run against the chip electrode for forming external connecting terminals, damage to the chip electrodes and an increase in cost of the mold can be prevented, and the package can be manufactured inexpensively without deteriorating the reliability.

Abstract: A method for fabricating a semiconductor device having LDD structure. The method includes: a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate; a second step for forming a conductive layer on said insulating layer; a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer; a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer; a fifth step for forming heavilyly doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer; a sixth step for removing said patterned photoresist layer; and a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

Abstract: In a semiconductor device having a resin-encapsulated structure, the width of an upper-mold portion of a package in a direction parallel to inner leads is made smaller than that of a lower-mold portion of the package so that the upper-mold portion cannot extend further towards outer leads than the lower-mold portion. Therefore, the amount of the positional deviation between an actual package region and a prospective package region is small and tiebars can be arranged close to the prospective package region in a lead frame. Since a fixed distance is ensured between the tiebars and the actual package region after molding, damage to the package is prevented during tiebar cutting. Since the amount of extension of any resin burr is small, a deflashing step is omitted.

Abstract: A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.

Abstract: A wafer cassette conveying system is capable of reducing a communication amount between a conveying device and a control device, further shortening the time period required for a movement of the conveying device. A control device 15, when receiving both of a lot carrying-in request signal outputted from a first treating device 11 and an empty cassette carrying-out request signal outputted from a second treating device 12, outputs a lot carrying-in command signal. A conveying device 20, when receiving this lot carrying-in command signal, conveys an actual cassette of the first treating device 11 to the second treating device 12 and also conveys an empty cassette of the second treating device 12 to an empty cassette space 14.