Abstract: The voltage reference generator of the present invention includes a plurality of p-channel transistors configured to act as resistors. Switching transistors, responsive to input signals, are utilized to bypass the resistors when in the "on" state, and enable the resistor when in the "off" state. Thus, when enabled, the resistors become part of a total resistance value in a branch of a voltage divider circuit. A minimum amount of space is used on an integrated circuit because the switching transistors are of the same type as the transistors which are configured to act as resistors.

Abstract: In a fuse programmable voltage generator providing an optimal internal voltage VCCINT, a counter outputs various values to a voltage down comparator to output corresponding internal voltages VCCINT until a desired voltage is obtained. Once the desired internal voltage VCCINT is determined, the counter is disabled and a fuse circuit is configured to substantially maintain the output of the desired internal voltage VCCINT.

Abstract: An output driver for a CMOS circuit minimizes latch-up. A P-channel transistor (14) has its source-drain path coupled in series with the source-drain path of one or more N-channel transistors (16, 12). An internally generated high voltage VCCP, higher than VCC, is applied to the moat, well, or region in which the P-channel transistor is formed, and is applied to the gate electrode of the N-channel transistor(s). In one embodiment (FIG. 3), the source of the P-channel transistor is connected directly to VCC whereas in another embodiment (FIGS. 1A/1B), it is coupled to the source-drain path of another N-channel transistor, the gate electrode of which is coupled to the high voltage VCCP. In such second embodiment, the drain of the second N-channel transistor is coupled to VCC, so that the P-channel transistor is in series between the two N-channel transistors.

Abstract: In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Abstract: A method and circuit improves the timing of a static column mode device by extending the valid write time to be equal to the write time in a fast page mode device. In particular, the circuit extends the global write enable signal and maintains the address in the address latch to increase the valid write time. Also, the circuit of the present invention improves the noise margin in the static column mode device by decoupling the write enable and column address strobe signals after they are initially received to ignore any noise in those signals. A timer is used.

Abstract: A method and circuit for configuring I/O devices, such as a DRAM or other memory device, uses master-slave buffer circuits in configurable I/O devices. When arranged in a master-slave arrangement, the slave data buffer is adapted to receive both input data and the output of an associated master circuit. In one configuration, each data buffer outputs data based upon the input data. In another configuration, each slave buffer outputs the output of an associated master buffer. The circuit of the present invention is preferably employed with a configurable I/O device incorporated in a lead-on-chip (LOC) package, although could be used in any configurable I/O device.

Abstract: A substrate bias generator avoids using a free-running oscillator and thereby saves power in the standby mode. A clock enable signal from a regulator sets a latch in a self-timed clock circuit. The latch setting initiates a first group of clock signals (that are used by a pump circuit for pumping), at the end of which the latch is reset but concomitantly an input circuit to the latch is disabled from recognizing a new pump signal. Resetting the latch causes the clock circuit to generate a second group of clock signals used in the charge pump to prepare fully for the next demand for pumping. At the end of the second group of clock signals, a full cycle of clocks has been completed in a self-timed manner, and the input circuit to the latch is reenabled to recognize a subsequent pump signal.

Abstract: A negative charge pump circuit for low voltage and wide voltage range applications. The charge pump includes two single-stage p-type pumps. One of the pumps is used to charge a circuit node down to a threshold voltage .vertline.Vt.sub.p .vertline. less than a desired voltage. When used in such a way, the other pump will charge a substrate to a full -VCC.

Abstract: A method of etching a polysilicon film specimen by an electronic cyclotron resonance etching technique or a microwave plasma etching technique includes the first process in which a mixed gas containing Cl.sub.2 and HBr is used as a process gas for etching, the Cl.sub.2 occupying 50-70 vol. % of the whole mixed gas; and the second process in which a mixed gas containing HBr and He is used, with HBr being in a proportion of 20-50 vol. % of the mixed gas, and a low bias voltage from -100 to -30 volts is applied to a specimen carrier. Further, in the first and second processes, a mixed gas containing HBr and He is used, with HBr being in a proportion of 20-50 vol. %, and a relatively high bias voltage from -250 to -100 volts is applied to the specimen carrier in the first process, while a low bias voltage from -100 to -30 volts is applied to the same in the second process. According to the present invention, a polysilicon film can be etched without causing undercut and with high dimensional accuracy.

Abstract: A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.

Abstract: A fast low-to-high voltage translator with immunity to latch-up. The circuit includes a voltage comparator and employs at least one transistor which is used to quickly pull up a node. If further uses another transistor which is capable of limiting the voltage at certain nodes in order to eliminate latch-up if a pumped power supply is provided to the circuit. Latch-up therefore is eliminated during power-up. Other transistors are utilized as voltage drop limiters to limit the voltage drop across other transistors during switching. This provides improved reliability by reducing substrate current and hot carriers.

Abstract: A supply circuit providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors which operate as a load to develop a voltage at first and second nodes. The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor, and to the gate electrode of a drive transistor and a third transistor. The drive transistor selectively couples operating voltage to the hold line. After the logic circuit turns off, the offset voltage which has been stored on the capacitor controls the drive transistor to couple the target holding voltage to the holding line.