Patents Assigned to Nippon Telegraph and Telephone Public Corporation
  • Patent number: 4507721
    Abstract: A floating type DC-DC converter for remote power feeding is connected via a power separating filter to a signal line on which an AC signal is superimposed on DC power. The DC power separated by the power separating filter is stored in an input capacitor and is supplied by a switching operation of a switching element to the primary winding of a transformer and AC power induced in its secondary winding is supplied to an output capacitor after being rectified by a rectifying element. An electrostatic shield layer is interposed between the primary and secondary windings of the transformer and is connected to the capacitor connected to one of the primary and secondary windings.
    Type: Grant
    Filed: July 21, 1983
    Date of Patent: March 26, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Seiichi Yamano, Haruo Ogiwara
  • Patent number: 4503807
    Abstract: A chemical vapor deposition apparatus has a reactor divided into a reaction space and a purging space by a susceptor for supporting a wafer and a loading chamber communicated through a gate with the reactor. Exhaust units are communicated with the reactor and loading chamber, respectively, so that the pressures in the reactor and loading chamber may be reduced. The susceptor has a plurality of recesses to aid placing or scooping the water. Through a transparent wall on the side of the purging space, the susceptor is heated by a lamp unit disposed outside the transparent wall. The loading chamber includes a wafer transport mechanism for charging a wafer into the reactor or discharging a processed wafer from the reactor. An unprocessed wafer is loaded to the loading chamber from a cassette and the processed wafer is unloaded to the cassette. One or a small number of wafers are processed at one time. A uniform film is deposited with a high reproducibility.
    Type: Grant
    Filed: May 29, 1984
    Date of Patent: March 12, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Satoshi Nakayama, Hideaki Takeuchi, Junichi Murota, Tatuhiko Hurukado, Shigeru Takeda, Masuo Suzuki, Harushige Kurokawa, Humihide Ikeda
  • Patent number: 4502143
    Abstract: An encoder for suppression of a consecutive identical digit in a digital transmission system has been found for facilitating the reproduction of a clock signal for regenerating reception data, and keeping the average signal level constant. According to the present invention, a single bit (x) is inserted for every predetermined number (m) of input digits, and said insertion bit is a complement of a digit of previous k bits where k is an integer satisfying 1.ltoreq.k.ltoreq.m. Preferably, the value k is 1. The present invention is useful for digital communication higher than 100 Mbits/second, in particular, in optical communication.
    Type: Grant
    Filed: April 19, 1982
    Date of Patent: February 26, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Masami Kato, Noriaki Yoshikai
  • Patent number: 4498063
    Abstract: In a switched capacitor filter of a first-order responsive to a filter input signal for producing a filter output signal by carrying out sampling operation at a predetermined sampling rate by the use of switching circuit, a capacitor, and an integrating circuit, a voltage divider produces a voltage divided signal in response to the filter input signal to reduce a total capacitance determined by capacitances of the capacitor and the integrating circuit. The voltage divided signal is sampled by the switching circuit to be sent to the integrating circuit at the sampling rate through the capacitor. The integrating circuit produces the filter output signal as a result of integration. In addition, an additional switched capacitor filter of a first-order is connected in cascade to the filter to form a switched capacitor filter of a second-order.
    Type: Grant
    Filed: January 17, 1983
    Date of Patent: February 5, 1985
    Assignees: Nippon Electric Co., Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Takayoshi Makabe, Yoshiaki Kuraishi, Kenji Nakayama, Tadakatsu Kimura
  • Patent number: 4497759
    Abstract: This invention discloses a continuous process for the production of polymer-polyoxymethylene (POM) having small linear expansion coefficients and high tensile modulus, the process for producing an ultrahigh modulus POM comprising the step of drawing a crystalline polymer continuously under dielectric heating while maintaining the ambient temperature at an elevated temperature by external heating, said ambient temperature being controlled to change from a lower temperature to a higher temperature along the drawing direction of said crystalline polymer with a pre-set temperature gradient.
    Type: Grant
    Filed: December 23, 1982
    Date of Patent: February 5, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Koichi Nakagawa, Osamu Maeda, Shinzo Yamakawa
  • Patent number: 4498195
    Abstract: A radio interference detection device for use in a multi-channel access angle-modulation radio system. A detecting system detects a received signal prior to angle demodulation and produces an AM component of the received signal which is then rectified. A determining section then determines the level of the rectified signal for use in detecting interference in accordance with a determination result. The determining section includes an angle demodulator for angle-demodulating the received signal, a first comparator for comparing the angle-demodulated signal and the rectified signal, a second comparator for producing the detection signal when the rectified signal exceeds a predetermined level and a gate for passing the output signal from the second comparator only when the angle-demodulated signal is smaller than the rectified signal.
    Type: Grant
    Filed: March 4, 1983
    Date of Patent: February 5, 1985
    Assignees: Nippon Telegraph & Telephone Public Corporation, Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tetsuo Ooi, Hiroshi Watanabe, Akio Gotoh, Shuitsu Tsutsumi, Ryohei Oba, Koichi Ito, Syouzi Huse
  • Patent number: 4492620
    Abstract: A plasma deposition apparatus comprising a plasma formation chamber into which a gas is introduced to produce plasma, a specimen chamber in which a specimen table is disposed for placing thereon a speciment substrate on which a thin film is to be formed, a plasma extraction window interposed between the plasma formation chamber and the specimen chamber, a target which is made of a sputtering material and is interposed between the plasma extraction window and the specimen table, a first means for extracting ions for sputtering the target from a plasma stream extracted from the plasma formation chamber to impinge against the target, and a second means for extracting the plasma stream through the plasma extraction window into the specimen chamber and for transporting the sputtered and ionized atoms to the specimen substrate period on the specimen table.
    Type: Grant
    Filed: September 9, 1983
    Date of Patent: January 8, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Seitaro Matsuo, Toshiro Ono
  • Patent number: 4491386
    Abstract: An optical fiber cable is described comprising a linear center member having at least one longitudinal and spiral groove in the surface thereof, one coated optical fiber received in each groove, an outer sheath that encloses the center member, and a jelly-like material with which the space around each optical fiber is entirely filled. A process for producing such an optical fiber cable is also described.
    Type: Grant
    Filed: August 31, 1981
    Date of Patent: January 1, 1985
    Assignees: Nippon Telegraph & Telephone Public Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Yukiyasu Negishi, Yukinori Ishida, Yasunori Saito, Shigeru Tanaka
  • Patent number: 4491958
    Abstract: In a speech synthesizer designed so that natural speech is chopped at constant intervals of time and characteristic parameters of the speech are extracted from the chopped speech and used for synthesis of speech, the number of bits of a characteristic parameter per analytical frame is not changed, but the interval of time of one analytical frame is changed to change the amount of information per unit time, while the time interval of one synthesis frame of the synthesizer is changed with the time interval of one analytical frame so that the time interval of one frame upon analysis and the time interval of one frame upon synthesis are made equal, whereby a single speech synthesizer can handle speech parameters of different amounts of information.
    Type: Grant
    Filed: October 22, 1981
    Date of Patent: January 1, 1985
    Assignees: Nippon Telegraph & Telephone Public Corporation, Hitachi, Ltd.
    Inventors: Kazuhiro Umemura, Tohru Sampei, Kazuo Nakata, Hirokazu Sato, Murakami Kenya, Kiyoshi Intoh
  • Patent number: 4491700
    Abstract: A hybrid circuit composed of semiconductor current amplifiers without an inductance and large capacitance has been found. The DC speech current supplied by the DC power source (33) and the speech signal from the modem (28) are adjusted by the current amplifiers (17a, 17b) so that the subscriber line (2) is terminated with the predetermined impedance (600 ohms), and the speech signal from the subscriber line (2) is transferred to the modem (28) through the AC monitor circuits (24a, 24b). The common mode noise induced on the subscriber line (2) is cancelled by adjusting the input current of said current amplifiers (17a, 17b) by the common mode noise detector (22) and the common mode noise monitor circuits (23a, 23b). The speech signal from the modem (28) to the subscriber line (2) does not return to the modem (28) because of the cancellation operation by the return signal detector circuit (32).
    Type: Grant
    Filed: November 25, 1981
    Date of Patent: January 1, 1985
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Toshiyuki Tahara, Hironobu Uehara, Kazuo Hamazato, Toshio Hayashi
  • Patent number: 4489241
    Abstract: An exposure method with an electron beam exposure apparatus in which an electron beam is emitted onto a substrate such as a silicon wafer on which an electron-beam sensitive resist is coated, thereby directly forming or writing patterns. A substrate having thereon a number of chips are divided into blocks, which each contain a plurality of chips. Marks are provided on each of the blocks, the positions of the marks are detected and the writing exposure positions of the chips within each block are modified on the basis of the detection results. According to this invention, efficient writing exposure can be made with high accuracy.
    Type: Grant
    Filed: June 9, 1982
    Date of Patent: December 18, 1984
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Tadahito Matsuda, Tsuneo Okubo, Susumu Ozasa, Norio Saitou, Haruo Yoda
  • Patent number: 4489340
    Abstract: A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the
    Type: Grant
    Filed: January 28, 1981
    Date of Patent: December 18, 1984
    Assignees: Nippon Telegraph & Telephone Public Corporation, Oki Electric Industry Co., Ltd.
    Inventors: Jun Ueda, Haruo Mori, Kazuo Hagimura, Hirokazu Tsukada, Kotaro Kato
  • Patent number: 4482821
    Abstract: A basic logic circuit of a superconductive logic circuit comprises a bridge circuit of four branches wherein first and second terminals are connected at least at two nodes and an output terminal is connected at least at a node. One branch of the bridge circuit comprises a series circuit consisting of a first resistor and a first Josephson junction connected between the first and second input terminals. The second branch comprises a parallel circuit of a second Josephson junction and a second resistor connected between the first input terminal and a grounding terminal of the bridge circuit. The third branch comprises a third resistor connected between the second input terminal and the output terminal. The fourth branch comprises a third junction connected between the output terminal and the grounding terminal. A load resistor is connected between the output terminal and the ground.
    Type: Grant
    Filed: June 3, 1981
    Date of Patent: November 13, 1984
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Kouji Houkawa, Akira Ishida, Masaru Okada
  • Patent number: 4480897
    Abstract: A single-polarization single mode optical fiber of the type comprising an elliptical core, a pair of stress applying parts on both sides of the minor radius of the elliptical core for applying asymmetrical stress thereto and a clad embedding therein the core and the stress applying parts, the stress applying parts being made of B.sub.2 O.sub.3 wherein a relative refractive index difference .DELTA. between the core and the clad satisfies a relation 0.004.ltoreq..DELTA..ltoreq.0.05, an ellipticity .epsilon. satisfies a relation 0.01.ltoreq..epsilon..ltoreq.0.9, the B.sub.2 O.sub.3 has a molar concentration of 1 to 25 mole %, ratio of thickness of the stress applying parts and the core is 5 to 15, a modal birefringence B expressed by an equation B=(.beta..sub.x -.beta..sub.y)/k satisfies a relation B=1.times.10.sup.-6 where (.beta..sub.x -.beta..sub.y) represents a propagation constant difference between HE.sub.11.sup.x and HE.sub.11.sup.
    Type: Grant
    Filed: June 15, 1982
    Date of Patent: November 6, 1984
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Katsunari Okamoto, Toshihito Hosaka, Yutaka Sasaki, Juichi Noda, Takao Edahiro
  • Patent number: 4475935
    Abstract: A method for producing an elongated optical fiber element is disclosed. The method envolves preparing two optical fiber elements by removing their outer coating layers to expose bare glass fiber portions. The glass fiber portions are melt-joint together. A material which is chemically compatible with the removed outered layer is then molded about the joined bare glass portions. A thermoplastic resin is then extruded continuously over the molded material in order to form a single elongated optical fiber element. The bonding method produces a structure which can withstand bending stress exerted on the coated optical fiber and prevent the concentration of any stress in the bonded area.
    Type: Grant
    Filed: July 22, 1982
    Date of Patent: October 9, 1984
    Assignees: Nippon Telegraph & Telephone Public Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Chihaya Tanaka, Kazuo Iwabuchi, Toshiaki Kakii, Yuichi Toda
  • Patent number: 4475174
    Abstract: In an apparatus for decoding a variable length code represented by a code tree, a decoding table memory is read out and the read out data is decided as to whether it is terminal or intermediate data. In the case of a terminal data, its decoded result information in the data is delivered out. In the case of an intermediate data, its data of the same number of bits as indicated by information of the data indicating the number of bits to be entered is entered from an input code train; this data and information of the intermediate data for determining an address of the decoding table memory to be accessed are added together to obtain the address of the memory to be accessed next; the address thus obtained is used to access the decoding table memory; and this operation is repeated until a terminal data is obtained.
    Type: Grant
    Filed: September 8, 1981
    Date of Patent: October 2, 1984
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventor: Hideaki Kanayama
  • Patent number: 4465967
    Abstract: A current supply circuit comprises a DC power feed circuit exhibiting a constant current characteristic for a power source and a constant resistance characteristic for a load, a first detecting circuit for detecting a load current or a load voltage, a DC-DC converter circuit inserted between the power source and the DC power feed circuit, a second detecting circuit for detecting an output voltage from the DC-DC converter circuit; and an operation circuit coupled at the input with the output of the first detecting circuit and the output of the second detecting circuit for controlling the DC-DC converter circuit by the output thereof. The DC-DC converter circuit is so controlled as to produce a voltage representative of the sum of a voltage drop across the load and a fixed voltage necessary for the operation of the DC power feed circuit.
    Type: Grant
    Filed: January 26, 1982
    Date of Patent: August 14, 1984
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Michio Tokunaga, Junjiro Kitano, Akio Sagawa, Toshio Hayashi, Kazuo Hamazato
  • Patent number: 4460998
    Abstract: In addition to a main memory device a spare memory device is provided. Both memory devices utilize word wires in common which are arranged to constitute matrix circuits together with groups of bit lines. When a bit error is contained in data read out from the main memory device, a correction circuit correcting the error and a register for storing the error are provided. An output of the register is used to switch a bit line from which the error has been detected to a corresponding bit line of the spare memory device.
    Type: Grant
    Filed: March 8, 1982
    Date of Patent: July 17, 1984
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Junzo Yamada, Tsuneo Mano, Junichi Inoue
  • Patent number: 4460417
    Abstract: An insulating film is prepared by oxidizing an amorphous silicon layer containing boron or boron and germanium. The amorphous silicon layer is partially oxidized inwardly from the surface of the amorphous silicon layer to form the insulating film, while the unoxidized portion of the amorphous silicon layer is used as a conductive layer. The amorphous silicon layer may contain boron or boron and an element of Group IV, for example germanium. The insulating film is utilized to fabricate a bipolar transistor.
    Type: Grant
    Filed: October 22, 1982
    Date of Patent: July 17, 1984
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Katsumi Murase, Teruo Tamama, Yoshihito Amemiya, Yoshihiko Mizushima
  • Patent number: 4460820
    Abstract: An apparatus for heating a heat-shrinkable tube has a base for supporting the heat-shrinkable tube and a plurality of heating units provided on the base. The heating units are independently operable and are disposed in the longitudinal direction of the heat-shrinkable tube.
    Type: Grant
    Filed: July 21, 1982
    Date of Patent: July 17, 1984
    Assignees: Nippon Telegraph & Telephone Public Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Michito Matsumoto, Toshiaki Kakii, Yuichi Toda