Abstract: A radio apparatus is configured to implement a method for computing a polar transformation of an input bit sequence of 2n bits for transmission by radio. The method comprises storing the input bit sequence in electronic memory as a working bit sequence, and then computing a bitwise XOR of a contiguous first half of the working bit sequence with a contiguous second half of the working bit sequence, the second half being disjoint from the first half. The result of the bitwise XOR is stored in electronic memory. A bit-interleave sequence is generated by interleaving the result of the bitwise XOR with the second half of the working bit sequence. Next, the bit interleave sequence is stored as the updated working bit sequence. After n iterations of the previous steps are performed, the working bit sequence, or a contiguous subsequence thereof, is the polar transformation of the input sequence.

Abstract: A first radio device is configured, for each of a plurality of further radio devices, to determine a respective connection interval and a respective periodic series of connection events, having a period equal to the connection interval, each connection event comprising time for transmitting data packets to the further radio device. The first radio device communicates the respective connection interval to each of the further radio devices. Before transmitting a first data packet of a connection event, over a radio channel, to a further radio device, the first radio device performs a clear channel assessment to determine whether the radio channel is clear, and, in response, before a start of the connection event, transmits a channel reservation signal over the radio channel until the start of the connection event. It then transmits the first data packet over the radio channel to the further radio device.

Abstract: There is disclosed a radio system, and a method for operating a radio system. An orthogonal frequency-division multiple-access (OFDMA) radio signal is transmitted, which has information digitally modulated onto it as OFDMA symbols on subcarriers in a first set of symbol periods. The radio signal has a second set of symbol periods interleaved, with the first set of symbol periods in time, in which these subcarriers are unmodulated, so as to create a predetermined temporal pattern. The radio signal is received on a first radio apparatus, which demodulates and uses information from the modulated symbol periods of the predetermined temporal pattern. A second radio apparatus receives the same radio signal, detects the predetermined temporal pattern of modulated and unmodulated symbol periods in the received radio signal, and, in response, activates its radio module by generating an electrical wake-up signal.

Abstract: A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.

Abstract: An electronic device comprises an oscillator circuit portion comprising an inverter and a crystal oscillator connected between the input and output terminals of the inverter. An amplitude regulator circuit portion is arranged to supply a current to the inverter. The amplitude regulator monitors a voltage at the input of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises a trimmable resistor arranged such that the voltage at the input of the inverter is set to an operating point when the supply current is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor. A current monitor is arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range.

Abstract: A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.

Abstract: A radio-frequency transceiver is operable to transmit one or more radio-frequency signals via an antenna in a transmitter mode and to receive one or more radio-frequency signals via the antenna in a receiver mode. The transceiver comprises a power amplifier for use in the transmitter mode comprising a switched-capacitor array comprising a plurality of capacitance elements, and a low-noise amplifier for use in the receiver mode. The transceiver is configured, when operating in the receiver mode, to pull one or more of the capacitance elements in the switched-capacitor array to a ground potential.

Abstract: An integrated-circuit device comprising a non-volatile memory (NVM), a debug port, and debug-port control circuitry for controlling access to the integrated-circuit device through the debug port. The debug-port control circuitry is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port at least partly in dependence on said determination.

Abstract: A circuit portion comprises a DCDC converter arranged to provide current from an output of the converter to one of a plurality of loads at a time. The plurality of loads includes a low priority load and a primary load. In response to the controller detecting, while the DCDC converter is providing current to the low priority load, that the voltage across the primary load is below a first threshold, channel logic circuitry is configured to stop providing current from the output of the converter to the low priority load and to provide current from the output of the converter to the primary load. A voltage regulator provides current to the low priority load when the voltage across the low priority load is below a second threshold.

Abstract: A switched capacitor power amplifier comprising a first, positive signal path and a second, negative signal path. The switched capacitor power amplifier is arranged to receive a digital control signal and, based on the digital control signal, to selectively activate both the first signal path and the second signal path, in a differential mode, to provide a first peak output power level, or either the first signal path or the second signal path, to produce a second peak output power level, wherein the second peak output power level is lower than the first output power level.

Abstract: A radio communication system, comprising a transmitter and a receiver wherein the transmitter is configured to transmit a multi-block request including control and timing information relating to a subsequent multi-block transmission, the receiver is configured to receive and decode said multi-block request, the transmitter is configured to subsequently transmit the multi-block transmission, wherein the multi-block transmission comprises a series of discrete blocks. Each block comprises a respective data payload and a synchronisation portion, and each synchronisation portion enables synchronisation between the transmitter and receiver when used in combination with the control and timing information, independently of receipt of other blocks in the multi-block transmission.

Abstract: According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Abstract: A digital radio receiver receives an encoded digital radio signal comprising a plurality of bits. The receiver determines a plurality of soft bits representing estimates of the bits and stores the soft bits in a rate de-matching buffer. The receiver calculates a first linear combination of soft bits from a first subset of the buffer and a second linear combination of soft bits from a second subset of the buffer. The receiver calculates a ratio between the first and second linear combinations and compares the ratio to an expected value. The receiver then determines its operational state based on the comparison.

Abstract: An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.

Abstract: This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.

Abstract: A method and circuitry for voltage regulation is provided. The circuitry has a voltage regulation portion and a control portion. The voltage regulation portion has a regulation mode and a bypass mode, and when the voltage regulation portion is in the bypass mode, it outputs an unregulated voltage received from a power supply. When the voltage regulation portion is in the regulation mode and the received unregulated voltage is greater than a received reference voltage, the voltage regulation portion regulates the unregulated voltage to output a predetermined regulated voltage. The control portion compares a feedback voltage based on the output from the voltage regulation portion to a reference voltage. When the voltage regulation portion is in the regulation mode, the control portion, in response to determining that the feedback voltage does not exceed the reference voltage, switches the voltage regulation portion into the bypass mode.

Abstract: A boost converter circuit is provided comprising an input arranged to receive an input voltage; an output arranged to generate a higher, output voltage for powering a further circuit portion; a switching arrangement arranged to control generation of the output voltage; and a control circuit portion arranged to monitor the input voltage and control the switching arrangement in response to the input voltage.

Abstract: An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.

Abstract: A method for determining a distance between an initiator radio transceiver and a reflector radio transceiver is provided. The method comprises the initiator radio transceiver transmitting a first radio signal at a first transmission time and the reflector radio transceiver receiving the first radio signal at a first reception time. The reflector transceiver samples the first radio signal using a sampling clock signal having a sampling period and determines a first reception-time value at a temporal resolution that is finer than the sampling period, including a fractional component representative of a fraction of the sampling period. The reflector transceiver transmits a second radio signal at a second transmission time that is offset from the sampling clock signal by an amount that depends on said fractional component so as to provide a predetermined dwell time that is determined to an accuracy finer than the sampling period.

Abstract: An oscillator circuit portion 200 including a resonator 216 arranged to oscillate with a resonant frequency, a capacitor 208 arranged to provide charge to the resonator, a first switch 206 arranged to connect the capacitor to an input voltage to charge the capacitor, a second switch 210 arranged to connect the resonator to the capacitor, and a timing circuit 202 configured to generate periodically a first pulse PULSE_L and a second pulse PULSE_H. The first pulse is configured to close the first switch, the second pulse is configured to close the second switch, and the first and second switches are arranged to be open when the timing circuit is not generating the first or second pulses, to maintain oscillation of the resonator.