Abstract: A circuit portion is provided which includes an energy harvesting device producing a DC output; a DC-DC converter having an input connected to the DC output of the energy harvesting device; an output for connection to a load; and a monitoring module including a non-ohmic semiconductor element. The monitoring module is arranged to derive information relating to an output current flowing from the DC-DC converter by measuring a current through the non-ohmic semiconductor element. The monitoring module is arranged to adjust one or more parameters of the DC-DC converter based on the information relating to said output current flowing from the DC-DC converter.

Abstract: Provided is a method for controlling the bias current, IPIERCE, of an oscillator. The method includes acquiring or determining a digital representation encoding a bias current. The method also includes carrying out an algorithm to update the digital representation if the oscillation amplitude is measured, by one or more peak detectors, to be outside of upper and lower thresholds. Also provided is an apparatus arranged to control the bias current of an oscillator using this method, the apparatus including one or more peak detectors and a current digital to analogue converter.

Abstract: An Orthogonal Frequency-Division Multiplexing digital radio transmitter is arranged to transmit a data packet comprising a plurality of Orthogonal Frequency-Division Multiplexing symbols. At least one of the symbols comprises a plurality of demodulation reference signals in a first plurality of frequency sub-carriers of the symbol. The transmitter is arranged to transmit a physical control channel at least partly distributed among a remainder of frequency sub-carriers of the symbol according to a calculated distribution. The transmitter calculates the distribution by arranging the remainder of frequency sub-carriers in a two-dimensional matrix such that said remainder of frequency sub-carriers have indices which are sequential in a first dimension and have a common increment in a second dimension, and allocating a second plurality of the remainder of frequency sub-carriers to the physical control channel sequentially in the second direction.

Abstract: There is provided a method of testing an RF transceiver circuit and an RF transceiver circuit arranged to be operable in a test mode including a transmitter circuit portion and a receiver circuit portion, the receiver circuit portion including a mixer. The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.

Abstract: A first radio transceiver device is configured for communication with a second radio transceiver device. It sends the second device, over a first radio connection, a connection establishment data packet comprising connection timing information for establishing a second radio connection and establishes the second connection. Each connection is associated with a respective time series of periodic connection events for radio transmissions. After the second connection has been established, the first device suspends the first connection by ceasing transmitting any data packets to the second device over the first connection. While the first connection is suspended, the first device can transmit to the second device, or receive from the second device, over the second connection, a data packet comprising an activation request, and, thereafter, activate the first connection by transmitting a data packet to the second device over the first connection in a connection event associated with the first connection.

Abstract: A radio-frequency modulator apparatus comprises a baseband stage, a mixer stage and a radio-frequency stage. The baseband stage comprises: an input line for receiving an input current representative of a baseband input signal, a baseband transistor that passes some or all of the input current between a first and a second terminal thereof, an electrical connection between the input line and a control terminal of the baseband transistor, and an output line connected to said control terminal. The mixer stage receives a signal from the baseband stage and mixes it with a radio-frequency local-oscillator signal to generate a radio-frequency mixed signal. The radio-frequency stage receives the radio-frequency mixed signal, applies the radio-frequency mixed signal to a control terminal of a radio-frequency transistor causing it to pass a radio-frequency output current between a first and a second terminal thereof, and outputs the radio-frequency output current as an output signal.

Abstract: A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.

Abstract: A system comprises a first circuit portion operating with a first clock having a first frequency, a second circuit portion operating with a second clock having a second, higher frequency, and an interface circuit portion for transferring data from the first and the second circuit portions. The first circuit portion is arranged to assert a data valid signal when asserting data at a data input. The data storage portion is configured to detect the data valid signal and to change an input data storage location of a shared memory in response thereto. The signalling portion is configured to change a state of an interface signal in response to the data valid signal. The data access portion is configured to change an output data storage location in response to the change of state of an interface signal and to output a data ready signal to the second circuit portion.

Abstract: A radio apparatus is configured to implement a method for computing a polar transformation of an input bit sequence of 2n bits for transmission by radio. The method comprises storing the input bit sequence in electronic memory as a working bit sequence, and then computing a bitwise XOR of a contiguous first half of the working bit sequence with a contiguous second half of the working bit sequence, the second half being disjoint from the first half. The result of the bitwise XOR is stored in electronic memory. A bit-interleave sequence is generated by interleaving the result of the bitwise XOR with the second half of the working bit sequence. Next, the bit interleave sequence is stored as the updated working bit sequence. After n iterations of the previous steps are performed, the working bit sequence, or a contiguous subsequence thereof, is the polar transformation of the input sequence.

Abstract: A first radio device is configured, for each of a plurality of further radio devices, to determine a respective connection interval and a respective periodic series of connection events, having a period equal to the connection interval, each connection event comprising time for transmitting data packets to the further radio device. The first radio device communicates the respective connection interval to each of the further radio devices. Before transmitting a first data packet of a connection event, over a radio channel, to a further radio device, the first radio device performs a clear channel assessment to determine whether the radio channel is clear, and, in response, before a start of the connection event, transmits a channel reservation signal over the radio channel until the start of the connection event. It then transmits the first data packet over the radio channel to the further radio device.

Abstract: There is disclosed a radio system, and a method for operating a radio system. An orthogonal frequency-division multiple-access (OFDMA) radio signal is transmitted, which has information digitally modulated onto it as OFDMA symbols on subcarriers in a first set of symbol periods. The radio signal has a second set of symbol periods interleaved, with the first set of symbol periods in time, in which these subcarriers are unmodulated, so as to create a predetermined temporal pattern. The radio signal is received on a first radio apparatus, which demodulates and uses information from the modulated symbol periods of the predetermined temporal pattern. A second radio apparatus receives the same radio signal, detects the predetermined temporal pattern of modulated and unmodulated symbol periods in the received radio signal, and, in response, activates its radio module by generating an electrical wake-up signal.

Abstract: A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.

Abstract: An electronic device comprises an oscillator circuit portion comprising an inverter and a crystal oscillator connected between the input and output terminals of the inverter. An amplitude regulator circuit portion is arranged to supply a current to the inverter. The amplitude regulator monitors a voltage at the input of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises a trimmable resistor arranged such that the voltage at the input of the inverter is set to an operating point when the supply current is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor. A current monitor is arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range.

Abstract: A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.

Abstract: A radio communication system, comprising a transmitter and a receiver wherein the transmitter is configured to transmit a multi-block request including control and timing information relating to a subsequent multi-block transmission, the receiver is configured to receive and decode said multi-block request, the transmitter is configured to subsequently transmit the multi-block transmission, wherein the multi-block transmission comprises a series of discrete blocks. Each block comprises a respective data payload and a synchronisation portion, and each synchronisation portion enables synchronisation between the transmitter and receiver when used in combination with the control and timing information, independently of receipt of other blocks in the multi-block transmission.

Abstract: A radio-frequency transceiver is operable to transmit one or more radio-frequency signals via an antenna in a transmitter mode and to receive one or more radio-frequency signals via the antenna in a receiver mode. The transceiver comprises a power amplifier for use in the transmitter mode comprising a switched-capacitor array comprising a plurality of capacitance elements, and a low-noise amplifier for use in the receiver mode. The transceiver is configured, when operating in the receiver mode, to pull one or more of the capacitance elements in the switched-capacitor array to a ground potential.

Abstract: An integrated-circuit device comprising a non-volatile memory (NVM), a debug port, and debug-port control circuitry for controlling access to the integrated-circuit device through the debug port. The debug-port control circuitry is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port at least partly in dependence on said determination.

Abstract: A circuit portion comprises a DCDC converter arranged to provide current from an output of the converter to one of a plurality of loads at a time. The plurality of loads includes a low priority load and a primary load. In response to the controller detecting, while the DCDC converter is providing current to the low priority load, that the voltage across the primary load is below a first threshold, channel logic circuitry is configured to stop providing current from the output of the converter to the low priority load and to provide current from the output of the converter to the primary load. A voltage regulator provides current to the low priority load when the voltage across the low priority load is below a second threshold.

Abstract: A switched capacitor power amplifier comprising a first, positive signal path and a second, negative signal path. The switched capacitor power amplifier is arranged to receive a digital control signal and, based on the digital control signal, to selectively activate both the first signal path and the second signal path, in a differential mode, to provide a first peak output power level, or either the first signal path or the second signal path, to produce a second peak output power level, wherein the second peak output power level is lower than the first output power level.

Abstract: According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.