Abstract: A digital radio receiver receives an encoded digital radio signal comprising a plurality of bits. The receiver determines a plurality of soft bits representing estimates of the bits and stores the soft bits in a rate de-matching buffer. The receiver calculates a first linear combination of soft bits from a first subset of the buffer and a second linear combination of soft bits from a second subset of the buffer. The receiver calculates a ratio between the first and second linear combinations and compares the ratio to an expected value. The receiver then determines its operational state based on the comparison.

Abstract: This document describes a solution for low-power voltage regulation. According to an aspect, there is provided an apparatus comprising: a supply voltage regulator circuit configured to regulate a power supply voltage of a circuit; a comparator circuit coupled to the power supply voltage and configured to sample the power supply voltage, to compare the sampled power supply voltage with a reference voltage and, if the sampled power supply voltage is below the reference voltage, to enable the supply voltage regulator circuit to charge the power supply voltage, wherein the comparator is switched on and off in response to a clock signal; and a clock signal generator circuit configured to generate the clock signal.

Abstract: An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.

Abstract: A boost converter circuit is provided comprising an input arranged to receive an input voltage; an output arranged to generate a higher, output voltage for powering a further circuit portion; a switching arrangement arranged to control generation of the output voltage; and a control circuit portion arranged to monitor the input voltage and control the switching arrangement in response to the input voltage.

Abstract: A method and circuitry for voltage regulation is provided. The circuitry has a voltage regulation portion and a control portion. The voltage regulation portion has a regulation mode and a bypass mode, and when the voltage regulation portion is in the bypass mode, it outputs an unregulated voltage received from a power supply. When the voltage regulation portion is in the regulation mode and the received unregulated voltage is greater than a received reference voltage, the voltage regulation portion regulates the unregulated voltage to output a predetermined regulated voltage. The control portion compares a feedback voltage based on the output from the voltage regulation portion to a reference voltage. When the voltage regulation portion is in the regulation mode, the control portion, in response to determining that the feedback voltage does not exceed the reference voltage, switches the voltage regulation portion into the bypass mode.

Abstract: A method for determining a distance between an initiator radio transceiver and a reflector radio transceiver is provided. The method comprises the initiator radio transceiver transmitting a first radio signal at a first transmission time and the reflector radio transceiver receiving the first radio signal at a first reception time. The reflector transceiver samples the first radio signal using a sampling clock signal having a sampling period and determines a first reception-time value at a temporal resolution that is finer than the sampling period, including a fractional component representative of a fraction of the sampling period. The reflector transceiver transmits a second radio signal at a second transmission time that is offset from the sampling clock signal by an amount that depends on said fractional component so as to provide a predetermined dwell time that is determined to an accuracy finer than the sampling period.

Abstract: An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.

Abstract: An electronic wireless communication device, comprising a memory region, storing a priority ordering of network identifiers, comprising at least a first wireless network identifier and a second wireless network identifier; and a network status indicator, having at least a first value and a second value. The electronic wireless communication device is arranged to carry out a network searching process, in which the electronic wireless communication device searches for available networks in an order defined by the priority ordering of network identifiers until an available network is identified and the electronic wireless communication device successfully connects to the available network. The electronic wireless communication device is arranged to omit at least the first network identifier from the priority ordering of network identifiers used during the network searching process whenever the network status indicator has the first value.

Abstract: An oscillator circuit portion 200 including a resonator 216 arranged to oscillate with a resonant frequency, a capacitor 208 arranged to provide charge to the resonator, a first switch 206 arranged to connect the capacitor to an input voltage to charge the capacitor, a second switch 210 arranged to connect the resonator to the capacitor, and a timing circuit 202 configured to generate periodically a first pulse PULSE_L and a second pulse PULSE_H. The first pulse is configured to close the first switch, the second pulse is configured to close the second switch, and the first and second switches are arranged to be open when the timing circuit is not generating the first or second pulses, to maintain oscillation of the resonator.

Abstract: An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

Abstract: An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.

Abstract: An electronic comparator circuit, including an input portion, an output portion, a first portion, a second portion and a gain portion. The input portion includes a first input transistor and a second input transistor. In the first portion a first terminal of a first input transistor is connected between a first terminal of a third transistor and a second terminal of a fourth transistor, wherein the fourth transistor is connected in a diode configuration. The second portion includes a first terminal of a second input transistor connected between a first terminal of a fifth transistor and a second terminal of a sixth transistor, wherein the sixth transistor is connected in a diode configuration. The gain portion includes a gate of a seventh gain transistor cross-coupled to a gate of the fifth transistor. A gate of an eighth gain transistor is cross-coupled to a gate of the third transistor.

Abstract: A radio frequency communication system is provided. The system comprises a first radio frequency device and a second radio frequency device arranged to establish a communication link by exchanging radio frequency signals in which data are encoded. The first radio frequency device is arranged to broadcast a radio frequency signal in which an advertising packet is encoded, the advertising packet comprising authentication information encrypted using an advertising key. The second radio frequency device is arranged to retrieve the authentication information and use the authentication information to authenticate the communication link.

Abstract: An integrated circuit comprises an oscillator which outputs a clock signal, a logic circuit portion, a detection circuit portion for detecting signal propagation delay relative to clock frequency, and a power supply which provides a configurable supply voltage. The detection circuit comprises a latch circuit portion, a delay circuit portion and a comparison circuit portion. The latch circuit portion outputs an alternating signal which changes state in dependence on the clock signal. This is received by the delay circuit portion which outputs first and second delayed signals respectively subject to first and second propagation delays each dependent on the supply voltage. The comparison circuit portion compares the alternating signal with the delayed signals, and outputs respective comparison signals if said signals indicate that the respective propagation delay is smaller than the clock signal period. A control circuit portion controls the supply voltage in dependence on the comparison signals.

Abstract: A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.

Abstract: An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.

Abstract: A method of synchronizing a plurality of client devices with an access point device comprises broadcasting by radio, from the access point, an encrypted broadcast message comprising synchronization information. The method further comprises receiving the encrypted broadcast message at each of the plurality of client devices, decrypting the encrypted broadcast message at each client device of the plurality of client devices, and using the synchronization information at each client device to synchronize the respective client device with the access point device.

Abstract: A circuit portion has an analog voltage supply module, a clock and a digital control module clocked by the clock. A bias voltage is applied to an analog voltage supply module so that it supplies a voltage to a node. The voltage is sampled at the node, at a signal edge of the clock, to obtain a sampled voltage. The sampled voltage is stored, the bias voltage to the analog voltage supply module is disabled and the sampled voltage is supplied to the node. A refresh signal is subsequently generated in response to at least one refresh criterion being met; and in response to the digital control module receiving the refresh signal, a refresh sequence is initiated. The refresh sequence includes re-applying the bias voltage to the analog voltage supply module; re-sampling the voltage at the node at a signal edge of the clock; and storing the re-sampled voltage.

Abstract: An integrated circuit comprising a detection circuit portion for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion comprises a shadow flip-flop comprising a clock input and a clock net connected to said clock input. The detection circuit portion also comprises a clock gate connected to the clock net that is controlled by an enable signal to selectively be in an open state in which the clock gate passes a clock signal to the clock net or in a closed state in which the clock gate does not pass the clock signal to the clock net. The detection circuit portion further comprises an error circuit portion, wherein the error circuit portion is arranged to selectively output an error signal if: the shadow flip-flop is clocked by a signal from the clock net and the clock gate is in the closed state.

Abstract: An electronic apparatus comprises a resistive random access memory (ReRAM) and hardware or software logic for reading from and writing to the ReRAM. The logic is configured, for a predetermined integer K>0 and for each word of a plurality of multi-bit words of length W bits stored at respective addresses in the ReRAM, to replace the respective word with a respective replacement value. The logic reads the word from the respective address in the ReRAM and uses a selection process to select K bits of the word. It stores the respective replacement value of length W bits at the respective address by writing to the address to flip the selected K of the bits of the word.