Abstract: An electronic wireless communication device, comprising a memory region, storing a priority ordering of network identifiers, comprising at least a first wireless network identifier and a second wireless network identifier; and a network status indicator, having at least a first value and a second value. The electronic wireless communication device is arranged to carry out a network searching process, in which the electronic wireless communication device searches for available networks in an order defined by the priority ordering of network identifiers until an available network is identified and the electronic wireless communication device successfully connects to the available network. The electronic wireless communication device is arranged to omit at least the first network identifier from the priority ordering of network identifiers used during the network searching process whenever the network status indicator has the first value.

Abstract: An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

Abstract: An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.

Abstract: A radio frequency communication system is provided. The system comprises a first radio frequency device and a second radio frequency device arranged to establish a communication link by exchanging radio frequency signals in which data are encoded. The first radio frequency device is arranged to broadcast a radio frequency signal in which an advertising packet is encoded, the advertising packet comprising authentication information encrypted using an advertising key. The second radio frequency device is arranged to retrieve the authentication information and use the authentication information to authenticate the communication link.

Abstract: An electronic comparator circuit, including an input portion, an output portion, a first portion, a second portion and a gain portion. The input portion includes a first input transistor and a second input transistor. In the first portion a first terminal of a first input transistor is connected between a first terminal of a third transistor and a second terminal of a fourth transistor, wherein the fourth transistor is connected in a diode configuration. The second portion includes a first terminal of a second input transistor connected between a first terminal of a fifth transistor and a second terminal of a sixth transistor, wherein the sixth transistor is connected in a diode configuration. The gain portion includes a gate of a seventh gain transistor cross-coupled to a gate of the fifth transistor. A gate of an eighth gain transistor is cross-coupled to a gate of the third transistor.

Abstract: An integrated circuit comprises an oscillator which outputs a clock signal, a logic circuit portion, a detection circuit portion for detecting signal propagation delay relative to clock frequency, and a power supply which provides a configurable supply voltage. The detection circuit comprises a latch circuit portion, a delay circuit portion and a comparison circuit portion. The latch circuit portion outputs an alternating signal which changes state in dependence on the clock signal. This is received by the delay circuit portion which outputs first and second delayed signals respectively subject to first and second propagation delays each dependent on the supply voltage. The comparison circuit portion compares the alternating signal with the delayed signals, and outputs respective comparison signals if said signals indicate that the respective propagation delay is smaller than the clock signal period. A control circuit portion controls the supply voltage in dependence on the comparison signals.

Abstract: An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.

Abstract: A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.

Abstract: A method of synchronizing a plurality of client devices with an access point device comprises broadcasting by radio, from the access point, an encrypted broadcast message comprising synchronization information. The method further comprises receiving the encrypted broadcast message at each of the plurality of client devices, decrypting the encrypted broadcast message at each client device of the plurality of client devices, and using the synchronization information at each client device to synchronize the respective client device with the access point device.

Abstract: A circuit portion has an analog voltage supply module, a clock and a digital control module clocked by the clock. A bias voltage is applied to an analog voltage supply module so that it supplies a voltage to a node. The voltage is sampled at the node, at a signal edge of the clock, to obtain a sampled voltage. The sampled voltage is stored, the bias voltage to the analog voltage supply module is disabled and the sampled voltage is supplied to the node. A refresh signal is subsequently generated in response to at least one refresh criterion being met; and in response to the digital control module receiving the refresh signal, a refresh sequence is initiated. The refresh sequence includes re-applying the bias voltage to the analog voltage supply module; re-sampling the voltage at the node at a signal edge of the clock; and storing the re-sampled voltage.

Abstract: An electronic apparatus comprises a resistive random access memory (ReRAM) and hardware or software logic for reading from and writing to the ReRAM. The logic is configured, for a predetermined integer K>0 and for each word of a plurality of multi-bit words of length W bits stored at respective addresses in the ReRAM, to replace the respective word with a respective replacement value. The logic reads the word from the respective address in the ReRAM and uses a selection process to select K bits of the word. It stores the respective replacement value of length W bits at the respective address by writing to the address to flip the selected K of the bits of the word.

Abstract: An integrated circuit comprising a detection circuit portion for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion comprises a shadow flip-flop comprising a clock input and a clock net connected to said clock input. The detection circuit portion also comprises a clock gate connected to the clock net that is controlled by an enable signal to selectively be in an open state in which the clock gate passes a clock signal to the clock net or in a closed state in which the clock gate does not pass the clock signal to the clock net. The detection circuit portion further comprises an error circuit portion, wherein the error circuit portion is arranged to selectively output an error signal if: the shadow flip-flop is clocked by a signal from the clock net and the clock gate is in the closed state.

Abstract: A start-up circuit for a self-biasing generator provides a reference voltage or a reference current, the start-up circuit including an impedance circuit. In response to a start-up signal input to the start-up circuit, the impedance circuit is coupled to a bias voltage line of a current mirror circuit of the self-biasing generator, thereby inducing current to flow in the self-biasing generator and starting the self-biasing generator. A bypass current source is coupled to the current mirror circuit and to the impedance. The bypass current source is configured to be driven by a current in the current mirror circuit and to supply current to the impedance in proportion to the current in the current mirror circuit, thereby limiting the current induced to the self-biasing generator by the start-up circuit.

Abstract: A circuit portion for filtering digital signals comprises a first delay circuit portion, a second delay circuit portion, and a logic circuit portion. The first delay circuit portion introduces a time delay to rising edges of an input signal and outputs a first delayed digital signal. The second delay circuit portion introduces a time delay to falling edges of the input signal and outputs a second delayed digital signal. The logic circuit portion outputs a signal which retains a current state when the first and second delayed signals have different states, and a state that is dependent on a state of the first and second delayed signals when the first and second delayed 10 signals have the same state. The circuit portion effectively removes glitches—i.e. pulses of short duration—from the input signal.

Abstract: A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

Abstract: A radio receiver apparatus comprises radio circuitry for receiving a sequence of radio data packets, transmitted at regular intervals, wherein the sequence of radio data packets encodes a digital audio stream and each radio data packet encodes a respective number of audio samples from the digital audio stream. The apparatus also comprises a digital audio interface for outputting audio samples from the received digital audio stream, a controllable oscillator arranged to control an output rate at which the audio samples are output from the digital audio interface, and a timer. The apparatus also comprises control logic, configured to use the timer to measure an interval between receiving each of a pair of the radio data packets, and to control the oscillator to vary the output rate incrementally, in a number of steps, while outputting the audio samples from one radio data packet. The number of steps, or the size of each step, or both, depends on the measured interval.

Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.

Abstract: A low noise amplifier comprising a first transconductance amplifier arranged to receive an input voltage at its input terminal and to generate an output current at its output terminal. A second transconductance amplifier is arranged such that its input terminal is connected to the input terminal of the first transconductance amplifier, and such that the output terminal of the second transconductance amplifier is connected to the input terminal of the second transconductance amplifier via a capacitive feedback network (C1).

Abstract: A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.

Abstract: A radio frequency receiver arranged to monitor for wake-up frames in a plurality of sample windows is provided. The wake-up frames are transmitted by a radio frequency transmitter in a sequence according to one or more sequence parameters including a wake-up interval between each wake-up frame of the sequence, and each sample window has a sample duration that is less than the wake-up interval. The sample windows occur in a pattern based on at least one of the one or more sequence parameters, such that the radio frequency receiver is arranged to detect at least one of the sequence of wake-up frames.