Abstract: Chemical mechanical planarization apparatuses with polishing assemblies that provide for the passive removal of slurry are provided. In accordance with an embodiment, a work piece polishing assembly comprises a polishing pad comprising a polishing surface and an exhaust aperture that extends through the polishing pad from the polishing surface and is configured to receive a slurry from the polishing surface. An underlying member is disposed underlying the polishing pad and comprises a peripheral surface. The underlying member comprises a channel that is in fluid communication with the aperture and that opens at the peripheral surface of the underlying member.

Abstract: Methods of lining and/or filling gaps on a substrate by creating flowable silicon oxide-containing films are provided. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrates and is then converted into a silicon oxide film. In certain embodiments, the methods involve using a catalyst, e.g., a nucleophile or onium catalyst, in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant. Also provided are methods of converting the flowable film to a solid dielectric film. The methods of this invention may be used to line or fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.

Abstract: Using UV radiation, methods to modify shallow trench isolation (STI) film tensile stress to generate channel strain without adversely impacting the efficiency of the transistor fabrication process are disclosed. Methods involve a two phase process: a deposition phase, wherein silanol groups are formed in the silicon dioxide film, and a bond reconstruction phase, wherein UV radiation removes silanol bonds and induce tensile stress in the silicon dioxide film.

Abstract: A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.

Abstract: Methods are provided for chemical mechanical planarization of a layer and for determining the endpoint of a CMP operation. In accordance with one embodiment the method for determining an endpoint comprises making a plurality of eddy current thickness measurement of the layer being planarized, each of the plurality of measurements spaced apart by a predetermined length of time. A difference is calculated between sequential ones of the plurality of eddy current measurements, and a predetermined minimum threshold for the difference is set. The endpoint is defined as a calculated difference less than the predetermined minimum threshold.

Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.

Abstract: Methods of forming a dielectric layer having a low dielectric constant and high mechanical strength are provided. The methods involve depositing a sub-layer of the dielectric material on a substrate, followed by treating the sub-layer with a plasma. The process of depositing and plasma treating the sub-layers is repeated until a desired thickness has been reached.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: Pad-assisted electropolishing of the substrate is conducted by performing anodic dissolution of metal at a first portion of the substrate and simultaneously mechanically buffing a second portion of the substrate with a buffing pad. Anodic dissolution includes forming a thin liquid layer of electropolishing liquid between the anodic substrate and a cathodic electropolishing head. The location of electrical contacts between the substrate and power supply allow peripheral edge regions of the substrate to be mechanically buffed with the pad. Preferably, a substrate is further planararized using an isotropic material-removal technique. An apparatus includes an electropolishing head that is movable to a position proximate to a first portion of a substrate to form a thin gap, and a buffing pad that mechanically buffs a second portion of the substrate using minimal pressure.

Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.

Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: Methods and apparatus for improving mechanical properties of a dielectric film on a substrate are provided. In some embodiments, the dielectric film is a carbon-doped oxide (CDO). The methods involve the use of modulated ultraviolet radiation to increase the mechanical strength while limiting shrinkage and limiting any increases in the dielectric constant of the film. Methods improve film hardness, modulus and cohesive strength, which provide better integration capability and improved performance in the subsequent device fabrication procedures such as chemical mechanical polishing (CMP) and packaging.

Abstract: Pad-assisted electropolishing of the substrate is conducted by performing anodic dissolution of metal at a first portion of the substrate and simultaneously mechanically buffing a second portion of the substrate with a buffing pad. Anodic dissolution includes forming a thin liquid layer of electropolishing liquid between the anodic substrate and a cathodic electropolishing head. The location of electrical contacts between the substrate and power supply allow peripheral edge regions of the substrate to be mechanically buffed with the pad. Preferably, a substrate is further planararized using an isotropic material-removal technique. An apparatus includes an electropolishing head that is movable to a position proximate to a first portion of a substrate to form a thin gap, and a buffing pad that mechanically buffs a second portion of the substrate using minimal pressure.

Abstract: Methods and apparatuses are provided for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. Such curves can reduce the number of wafers used in the calibration of the sensors while providing higher accuracy over a larger thickness range. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: A system and method for that allows one part of an atomic layer deposition (ALD) process sequence to occur at a first temperature while allowing another part of the ALD process sequence to occur at a second temperature. In such a fashion, the first temperature can be chosen to be lower such that decomposition or desorption of the adsorbed first reactant does not occur, and the second temperature can be chosen to be higher such that comparably greater deposition rate and film purity can be achieved. Additionally, the invention relates to improved temperature control in ALD to switch between these two thermal states in rapid succession.

Abstract: Methods of forming dielectric films with increased density and improved film properties are provided. The methods involve exposing dielectric films to microwave radiation. According to various embodiments, the methods may be used to remove hydroxyl bonds, increase film density, reduce or eliminate seams and voids, and optimize film properties such as dielectric constant, refractive index and stress for particular applications. In certain embodiments, the methods are used to form conformal films deposited by a technique such as PDL. The methods may be used in applications requiring low thermal budgets.