Patents Assigned to Novellus Systems
  • Patent number: 7223707
    Abstract: A method for using ALD and RVD techniques in semiconductor manufacturing to produce a smooth nanolaminate dielectric film, in particular for filling structures with doped or undoped silica glass, uses dynamic process conditions. A dynamic process using variable substrate (e.g., wafer) temperature, reactor pressure and/or reactant partial pressure, as opposed to static process conditions through various cycles, can be used to minimize film roughness and improve gap fill performance and film properties via the elimination or reduction of seam occurrence. Overall film roughness can be reduced by operating the initial growth cycle under conditions which optimize film smoothness, and then switching to conditions that will enhance conformality, gap fill and film properties for the subsequent process cycles. Film deposition characteristics can be changed by modulating one or more of a number of process parameters including wafer temperature, reactor pressure, reactant partial pressure and combinations of these.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 29, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Jeff Tobin, Ron Rulkens, Dennis M. Hausmann, Adrianne K. Tipton, Raihan M. Tarafdar, Bunsen Nie
  • Patent number: 7217398
    Abstract: A reactor vessel is provided with a solvent in a supercritical PVT state for use in depositing films on a deposition substrate. A metal organic precursor is dissolved in the supercritical solvent, as is a reaction agent. A chemical reaction deposits a film, such as a metal film on a semiconducting wafer, and reaction byproducts including a ligand ensue from the chemical reaction. Effluent from the reactor vessel is submitted to a precursor-forming agent that reacts with the ligand to rejuvenate the precursor. Alternatively, the precursor-forming agent can be used for point-of-use formation of the precursor with or without recycle of reaction byproducts.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: May 15, 2007
    Assignee: Novellus Systems
    Inventors: Jason Blackburn, Jeremie Dalton
  • Patent number: 7217658
    Abstract: High density plasma chemical vapor deposition and etch back processes fill high aspect ratio gaps without liner erosion or further underlying structure attack. The characteristics of the deposition process are modulated such that the deposition component of the process initially dominates the sputter component of the process. For example, reactive gasses are introduced in a gradient fashion into the HDP reactor and introduction of bias power onto the substrate is delayed and gradually increased or reactor pressure is decreased. In the case of a multi-step etch enhanced gap fill process, the invention may involve gradually modulating deposition and etch components during transitions between process steps. By carefully controlling the transitions between process steps, including the introduction of reactive species into the HDP reactor and the application of source and bias power onto the substrate, structure erosion is prevented.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 15, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Atiye Bayman, George D. Papasouliotis, Yong Ling, Weijie Zhang, Vishal Gauri, Mayasari Lim
  • Patent number: 7214630
    Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: May 8, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, James S. Sims, Akhil Singhal
  • Patent number: 7211509
    Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc,
    Inventors: Sanjay Gopinath, Jeremie Dalton, Jason M. Blackburn, John Drewery, Willibrordus Gerardus Maria van den Hoek
  • Patent number: 7211525
    Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Sunil Shanker, Sean Cox, Chi-I Lang, Judy H. Huang, Minh Anh Nguyen, Ken Vo, Wenxian Zhu
  • Patent number: 7211186
    Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7211175
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 7211174
    Abstract: Systems and methods to provide electrical contacts to a workpiece to facilitate electrotreating processes, including electroplating and electroetching processes are presented.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M Basol, Homayoun Talieh, Boguslaw A. Nagorski, Cyprian E. Uzoh, Jeffrey A. Bogart
  • Patent number: 7208389
    Abstract: Methods of preparing a porous low-k dielectric material on a substrate are provided. The methods involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film, leaving a porous low-k dielectric matrix. Methods using oxidative conditions and non-oxidative conditions are described. The methods described may be used to remove porogen from porogen-containing precursor films. The porogen may be a hydrocarbon such as a terpene (e.g., alpha-terpinene) or a norbornene (e.g., ENB). The resulting porous low-k dielectric matrix can then be annealed to remove water and remaining silanols capped to protect it from degradation by ambient conditions, which methods will also be described.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: April 24, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Adrianne K. Tipton, Brian G. Lu, Patrick A. Van Cleemput, Michelle T. Schulberg, Qingguo Wu, Haiying Fu, Feng Wang
  • Patent number: 7204743
    Abstract: A system for processing a conductive surface on a front surface of a wafer to form a metallic interconnect structure is disclosed. The system for processing comprises an electrochemical mechanical processing (ECMPR) module configured to form a substantially planarized conductive layer on the front surface of the wafer, a chamber within the ECMPR module configured to remove conductive material from an edge region of the wafer, a CMP module configured to receive the wafer from the ECMPR module and polish the planarized conductive layer on the surface of the wafer to form the metallic interconnect structure, and a robot configured to transfer the wafer from the ECMPR module to the chemical mechanical polish (CMP) module. In one aspect of the invention, the ECMPR module deposits conductive material on the front surface of the wafer. The ECMPR module removes at least a portion of the conductive layer from the front surface of the wafer.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: April 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7204924
    Abstract: The present invention provides a method for forming a conductive film with uniform properties on a wafer surface that has features or cavities. During the process, the workpiece is rotated and laterally moved while an electrodeposition solution is delivered onto the wafer surface at a predetermined flow rate, and a potential difference is applied between the workpiece surface and the electrode. The workpiece is rotated about an axis at predetermined revolutions per minute so that an edge region of the workpiece has a first predetermined linear velocity due to the rotation. The workpiece has a second predetermined linear velocity due to the lateral motion. The second predetermined velocity may be larger than the first predetermined velocity. Further, the wafer may not be rotated.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: April 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Homayoun Talieh
  • Patent number: 7204917
    Abstract: The present invention is directed to a top surface of a workpiece surface influencing device and a method of using the same. The top surface of the workpiece surface influencing device is adapted for use in an electrochemical mechanical processing apparatus in which a solution becomes disposed onto a conductive surface of a workpiece and electrochemical mechanical processing of the conductive surface is performed while relative movement and physical contact exists between the top surface and the conductive surface. The top surface comprises a ceramic material that presents a substantially planar contact area to the conductive surface, the ceramic material having a hardness greater than that of the conductive surface. A plurality of channels are formed through the top surface.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: April 17, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Cyprian E. Uzoh, Bulent M. Basol
  • Patent number: 7201828
    Abstract: An apparatus for performing an electrochemical process on a surface of a workpiece comprises a platen assembly comprising a support platen, an electrolyte distribution plate, and a first conductive layer intermediate the support platen and distribution plate and configured to be coupled to at least a first potential. A carrier is configured to carry the workpiece and position the workpiece proximate the electrolyte distribution plate. A reservoir delivers an electrolyte to the electrolyte distribution plate. At least one contact separate from the platen assembly engages a peripheral region of the workpiece for coupling the workpiece to a second potential.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: April 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventor: Ismail Emesh
  • Patent number: 7202176
    Abstract: The present invention pertains to methods for removing unwanted material from a work piece. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer during semiconductor manufacturing. Methods involve implementing a hydrogen plasma operation with downstream mixing with an inert gas. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: April 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Haruhiro Harry Goto, David Cheung, Prabhat Kumar Sinha
  • Patent number: 7202185
    Abstract: An method employing atomic layer deposition (ALD) and rapid vapor deposition (RVD) techniques conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant and a high degree of surface smoothness. The method includes the following three principal operations: exposing a substrate surface to an aluminum-containing precursor gas to form a saturated layer of aluminum-containing precursor on the substrate surface; exposing the substrate surface to an oxygen-containing gas to oxidize the layer of aluminum-containing precursor; and exposing the substrate surface to a silicon-containing precursor gas to form the dielectric film. Generally an inert gas purge is employed between the introduction of reactant gases to remove byproducts and unused reactants. These operations can be repeated to deposit multiple layers of dielectric material until a desired dielectric thickness is achieved.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: April 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Dennis M. Hausmann, Jeff Tobin, George D. Papasouliotis, Ron Rulkens, Raihan M. Tarafdar, Adrianne K. Tipton, Bunsen Nie
  • Patent number: 7201829
    Abstract: The present invention includes a mask plate design that includes at least one or a plurality of channels portions on a surface of the mask plate, into which electrolyte solution will accumulate when the mask plate surface is disposed on a surface of wafer, and out of which the electrolyte solution will freely flow. There are also at least one or a plurality of polish portions on the mask plate surface that allow for polishing of the wafer when the mask plate surface is disposed on a surface of wafer.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: April 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Cyprian Uzoh, Jeff A. Bogart
  • Patent number: 7198545
    Abstract: Methods are provided for calibrating a tool using an eddy current probe and calibration wafers that each have a measurable predetermined property and a measurement of the measurable predetermined property of a first calibration wafer is different than a measurement of the measurable predetermined property of a second calibration wafer. The methods include determining a first set of impedance measurements of the calibration wafers while each is disposed in the tool and the tool has a tool parameter that is at a first condition, collecting a second set of impedance measurements of the calibration wafers while each is disposed in the tool and the tool parameter is at a second condition, establishing a reference point, based upon a first and a second data point from the first set of impedance measurements and a first and a second data point from the second set of impedance measurements.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: April 3, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Tatyana Korovina, legal representative, Robert J. Stoya, Nikolay Korovin, deceased
  • Patent number: 7199048
    Abstract: Methods and structures are provided for conformal lining of dual damascene structures in semiconductor devices that contain porous or low k dielectrics. Features, such as trenches and contact vias are formed in the dielectrics. The features are subjected to low-power plasma predeposition treatment to irregularities on the porous surfaces and/or reactively form an permeation barrier before a diffusion barrier material is deposited on the feature. The diffusion barrier may, for example, be deposited by CVD using metalorganic vapor reagents. The feature is then filled with copper metal and further processed to complete a dual damascene interconnect. The plasma predeposition treatment advantageously reduces the amount of permeation of the metalorganic reagent into the interlayer dielectric.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: April 3, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Karen Chu, Anil Vijayendran, Michal Danek
  • Patent number: 7195548
    Abstract: A method and apparatus are provided for post-CMP cleaning of a semiconductor work piece. The method comprises the steps of subjecting the work piece to a first cleaning composition having one of an acidic pH and a basic pH and subjecting the work piece to a second cleaning composition having an acidic pH, if the first cleaning composition has a basic pH and subjecting the work piece to a second cleaning composition having a basic pH, if the first cleaning composition has an acidic pH.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 27, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwas V. Hardikar, James A. Schlueter, Guangshun Chen