Abstract: A non-volatile memory cell and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor element coupled to the antifuse element and configured to provide one or more voltage pulses to the programming node. The antifuse element is configured to have a changed resistivity after the programming node is subjected to the one or more voltage pulses, the change in resistivity representing a change in logic state. The antifuse element comprises a MOS transistor, its gate being coupled to one of the programming node and a control node, and its source and drain being coupled to the other one of the programming node and the control node. The MOS transistor is formed in a well and the source, drain and well are coupled to the same voltage level.

Abstract: A multiple time programmable non-volatile memory element and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The multiple time programmable non-volatile memory element includes a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.

Abstract: A non-volatile memory cell including an antifuse element having a programming node and a control node, a capacitor element, a precharge element, an access element, and a leakage element. The antifuse element is configured to have changed resistivity (representing a change in logic state) after the programming node is subjected to one or more voltage pulses. The capacitor element, coupled to the programming node, is configured to provide the one or more voltage pulses to the programming node. The precharge element, coupled to the programming node, is configured to increase the one or more voltage pulses provided to the programming to node. The access element, coupled to the control node, is configured to allow determination of the logic state of the antifuse element based on current flow through the access element. The leakage element is coupled to the control node and configured to modify the current flowing through the access element when the resistivity of the antifuse element has not been changed.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other intergrated curcuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. A capacitor element is used to provide programming voltages to the non-volatile memory cell. And in one embodiment, the non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node, such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses with the change in resistivity representing a change in logic state, and such that the capacitor element is configured to provide the voltage pulses to the programming node.