Abstract: A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

Abstract: The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

Abstract: A supply voltage detecting circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives and detects a supply voltage and is used to detect to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is higher than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a constant current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the constant current.

Abstract: A system on chip including a first master circuit, a second master circuit, a routing circuit, a bridge control circuit, and a peripheral circuit is provided. The first master circuit provides a first command. The second master circuit provides a second command. The routing circuit receives the first command and the second command and provides an output command. The bridge control circuit receives the output command and stores an attribute setting value. In response to the routing circuit receiving the first command and the first command pointing to the peripheral circuit, the routing circuit uses the first command as the output command and the bridge control circuit determines whether attribute information of the output command matches the attribute setting value. In response to the attribute information of the output command matching the attribute setting value, the bridge control circuit provides the output command to the peripheral circuit.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

Abstract: A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Abstract: A motor control device and a motor control method are provided. The motor control device includes a memory and a controller. During an initialization period, the controller drives a brushless DC motor to change a rotor position through a drive circuit for adjusting and obtaining a starting angle and a locked exciting current corresponding to the starting angle, and the controller stores starting-angle information corresponding to the starting angle and locked exciting-current information corresponding to the locked exciting current in the memory. After the initialization period ends, during a normal rotation period, the controller maintains the rotor position of the brushless DC motor at the starting angle with the locked exciting current through the drive circuit, until the controller activates the brushless DC motor through the drive circuit.

Abstract: A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Abstract: A solid-state imaging apparatus includes pixel cells arranged in a matrix. Each pixel cell includes: a first photodiode that accumulates a signal charge generated by photoelectric conversion; a second photodiode that functions as a first holder that holds a signal charge that overflows from the first photodiode; a second holder; and a first transfer transistor that transfers the signal charge held in the second photodiode to the second holder.

Abstract: A sensor is provided and is disposed on a package body of an integrated circuit chip. The sensor includes a sensing element, a protective element, a cover, and at least two traces. The sensing element is disposed on the integrated circuit chip. The protective element is disposed on the integrated circuit chip and surrounds the sensing element. The cover is connected to the protective element. The at least two traces are electrically connected to the sensing element and to at least two pins of the integrated circuit chip.

Abstract: A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: A method for measuring an input capacitance of a pin of an electronic device includes, using a tester including Pin Electronics (PE), obtaining a first capacitance measurement while the pin is disconnected from the PE, and a second capacitance measurement while the pin is connected to the PE. The input capacitance of the pin is calculated from the first and second capacitance measurements.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Abstract: An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

Abstract: An illumination device includes a first light source that emits first light having a first peak wavelength which is highest in intensity in a wavelength range from near-ultraviolet to green in an emission spectrum; a second light source that emits second light having a second peak wavelength which is highest in intensity in a wavelength range from near-ultraviolet to green in an emission spectrum, the second light illuminating a position identical to a position illuminated by the first light; and a detection device that detects whether an object is present at a given position, wherein the second peak wavelength is shorter than the first peak wavelength, and a luminous flux of the first light is decreased and a luminous flux of the second light is increased when the detection device detects that the object is present at the predetermined position.