Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.

Abstract: A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.

Abstract: A semiconductor device includes a metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT) and a Schottky gate HEMT. The Schottky gate HEMT and the MISHEMT are connected in series, and a Schottky gate of the Schottky gate HEMT is electrically connected with the source of the MISHEMT so as to generate a forward diode from the source to the drain of the MISHEMT. The series-connected structure is good for increasing the breakdown voltage of the semiconductor device, and the forward diode can reduce the power loss.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.

Abstract: A semiconductor device includes: a channel layer not containing Al; a barrier layer above the channel layer containing Al; a recess; and an ohmic electrode in the recess, which is in ohmic contact with a two-dimensional electron gas layer. An Al composition ratio distribution of the barrier layer has a maximum point at a first position. The semiconductor device includes: a first inclined surface of the barrier layer which includes the first position and is in contact with the ohmic electrode; and a second inclined surface of the barrier layer which intersects the first inclined surface on a lower side of the first inclined surface, and is in contact with the ohmic electrode. To the surface of the substrate, an angle of the second inclined surface is smaller than an angle of the first inclined surface. A position of the first intersection line is lower than the first position.

Abstract: A management controller is coupled to a plurality of external devices. The management controller includes a control circuit and a transmission circuit. The control circuit generates a control signal according to a first counting value and a second counting value. The transmission circuit is coupled to the external devices. In response to the first counting value not being equal to a first target value, the transmission circuit enters a circulating mode according to the control signal. In the circulating mode, the transmission circuit triggers the external devices in order. In response to the second counting value not being equal to a second target value, the transmission circuit continues to operate in the circulating mode. In response to the second counting value being equal to the second target value, the transmission circuit exits the circulating mode.

Abstract: A power converter is provided. The power converter includes a switched-capacitor conversion circuit and an inductor buck circuit. The switched-capacitor conversion circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage to an intermediate voltage. The inductor buck circuit is coupled to an output terminal of the switched-capacitor conversion circuit to receive the intermediate voltage and operates at a constant on-time to generate an output voltage at a conversion output terminal according to the intermediate voltage. The inductor buck circuit includes an inductor. In response to that a state of an inductor current used for charging the inductor corresponds to a predetermined condition, a switching action of the switching operation is enabled, so that the switched-capacitor conversion circuit is switched from a first turned-on state to a second turned-on state.

Abstract: Methods and systems provide for modulating light sources in panel displays of devices, such as light emitting diodes (LEDs), to provide indications as to device performance. The modulations are at low and high frequencies. The low frequencies provide visible blinking patterns, indicative of an event in the device, and the high frequencies, provide non-visible blinking patterns, indicative of one or more parameters associated with the event.

Abstract: A continuous memory access acceleration circuit, an address shift circuit, and an address generation method are provided. An arithmetic circuit calculates a memory access address according to temporary data provided by a register circuit. A counter provides a count value. A counting control circuit controls the counter to accumulate the count value according to access times of a memory. An adder circuit adds the memory access address and the count value to generate a target memory access address.

Abstract: Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.

Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.

Abstract: A parameter checking method includes substituting a plurality of initial parameters into a data integrity algorithm to obtain syndrome data using a processor, and using a hardware cipher to calculate a calculation result based on the data integrity algorithm based on a plurality of calculation parameters corresponding to the initial parameters. Moreover, when the processor determines that the syndrome data is not the same as the calculation result, the processor outputs a hacker attack message, indicating that at least one of the calculation parameters has been tampered with.

Abstract: A power supply device for providing a driving voltage of an encryption/decryption device. When the encryption/decryption device is in operation and its driving voltage falls within the voltage range formed by an upper limit voltage and a lower limit voltage, only a supply voltage provided by a secure power supply device is used as the driving voltage for the encryption/decryption device. When the encryption and decryption device is in operation and its driving voltage falls outside the voltage range formed by the upper limit voltage and the lower limit voltage, the supply voltage and a stable voltage provided by the stable voltage source are used as the driving voltage at the same time, the supply voltage is further adjusted until the driving voltage falls within the voltage range formed by the upper limit voltage and the lower limit voltage, and then continue to use only the supply voltage as the driving voltage.

Abstract: A battery control system is provided with battery monitoring control circuits for measuring an output voltage of an individual or secondary battery cells, which are connected in an assembled battery divided into blocks; and a control circuit for controlling the battery monitoring control circuits. Each of the batter monitoring control circuits includes a communication interface for communications between the battery monitoring control circuits or communications with the control circuit; a power converter for converting a start-up signal into a DC voltage; and a start-up circuit that receives the DC voltage and generates a start-up control signal for starting the battery monitoring control circuit.

Abstract: A semiconductor laser element that includes a semiconductor layer including a waveguide formed in an intra-layer direction of the semiconductor layer and a window region formed in a front-side end face of the waveguide, has a current-laser optical output characteristic in which, at an operating temperature of 25° C.±3° C., a laser optical output has a maximum value at a first driving current value and the laser optical output is at most 20% of the maximum value at a second driving current value greater than the first driving current value, and is not damaged at the second driving current value.

Abstract: An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

Abstract: An imaging apparatus includes a light emitter, a pixel section, and a signal processor which calculates distance information of a subject. The pixel section includes a photoelectric converter, first and second read-out gates, and a plurality of charge accumulators including a first charge accumulator and a second charge accumulator. The first read-out gate is activated in a first period and deactivated in a second period. The second read-out gate is activated in the first period and the second period. The signal processor calculates the distance information based on a total amount of signal charges accumulated in the charge accumulators in the first period and the second period and a difference between an amount of signal charges accumulated in the second charge accumulator in the first period and the second period and an amount of the signal charge accumulated in the first charge accumulator in the first period.

Abstract: A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.